From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F5F21F3B9E for ; Tue, 7 Oct 2025 15:06:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759849617; cv=none; b=L4cifZL9LffHCVFC1lkqQRB8C+xJdkH2GIELYm6oBy6HARDWHLp7oTg7av7NLtE3vseB8QYnbQykDfDCr8h8bi6JB0aos1keuZJkR0n7sfaQ4U9Yh5cbi9/qFpbvT5Sym7hYQloGrktKBLx+ku3xtezbhh5rRPqELEO8q+vwkiA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759849617; c=relaxed/simple; bh=++vkDdKri2G/84Xuas4kaollScSVkT7SOgMcHmvpzwg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rGDFIR1M/OoLhoZnh2S3CYmpVCAdBA8Jp0Un9BxNcN08mUPDaLhk4ZruR4HFBxt5Kz8JYl/klgP20g7DJUiqpOcrZlDplf2PhtVU26K1ucPZZXaTG79Nh1UEVD5/9WF99rDJ0vuPJNfd3DPq4/VicaSub1ynZUcxVom2xxQF308= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAFC5C4CEF1; Tue, 7 Oct 2025 15:06:55 +0000 (UTC) Date: Tue, 7 Oct 2025 16:06:53 +0100 From: Catalin Marinas To: Lorenzo Pieralisi Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sascha Bischoff , Will Deacon , Mark Rutland , Marc Zyngier Subject: Re: [PATCH v2] arm64/sysreg: Fix GIC CDEOI instruction encoding Message-ID: References: <20251007102600.879337-1-lpieralisi@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251007102600.879337-1-lpieralisi@kernel.org> On Tue, Oct 07, 2025 at 12:26:00PM +0200, Lorenzo Pieralisi wrote: > The GIC CDEOI system instruction requires the Rt field to be set to 0b11111 > otherwise the instruction behaviour becomes CONSTRAINED UNPREDICTABLE. > > Currenly, its usage is encoded as a system register write, with a constant > 0 value: > > write_sysreg_s(0, GICV5_OP_GIC_CDEOI) > > While compiling with GCC, the 0 constant value, through these asm > constraints and modifiers ('x' modifier and 'Z' constraint combo): > > asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); > > forces the compiler to issue the XZR register for the MSR operation (ie > that corresponds to Rt == 0b11111) issuing the right instruction encoding. > > Unfortunately LLVM does not yet understand that modifier/constraint > combo so it ends up issuing a different register from XZR for the MSR > source, which in turns means that it encodes the GIC CDEOI instruction > wrongly and the instruction behaviour becomes CONSTRAINED UNPREDICTABLE > that we must prevent. > > Add a conditional to write_sysreg_s() macro that detects whether it > is passed a constant 0 value and issues an MSR write with XZR as source > register - explicitly doing what the asm modifier/constraint is meant to > achieve through constraints/modifiers, fixing the LLVM compilation issue. > > Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support") > Suggested-by: Catalin Marinas > Signed-off-by: Lorenzo Pieralisi > Acked-by: Marc Zyngier > Cc: stable@vger.kernel.org > Cc: Sascha Bischoff > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Marc Zyngier Reviewed-by: Catalin Marinas (unless Will sends another pull request before -rc1, I'll pick this patch shortly after)