Re: [PATCH v13 03/17] preempt: Introduce HARDIRQ_DISABLE_BITS

Boqun Feng
2025-10-31T19:59:32Z

On Fri, Oct 31, 2025 at 03:59:34PM +0100, Andreas Hindborg wrote:
> Lyude Paul <lyude@redhat.com> writes:
>
> > From: Boqun Feng <boqun.feng@gmail.com>
> >
> > In order to support preempt_disable()-like interrupt disabling, that is,
> > using part of preempt_count() to track interrupt disabling nested level,
> > change the preempt_count() layout to contain 8-bit HARDIRQ_DISABLE
> > count.
> >
> > Note that HARDIRQ_BITS and NMI_BITS are reduced by 1 because of this,
> > and it changes the maximum of their (hardirq and nmi) nesting level.
> >
> > Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
> > ---
> > include/linux/preempt.h | 11 +++++++++--
> > 1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/linux/preempt.h b/include/linux/preempt.h
> > index 9580b972e1545..bbd2e51363d8f 100644
> > --- a/include/linux/preempt.h
> > +++ b/include/linux/preempt.h
> > @@ -17,6 +17,8 @@
> > *
> > * - bits 0-7 are the preemption count (max preemption depth: 256)
> > * - bits 8-15 are the softirq count (max # of softirqs: 256)
> > + * - bits 16-23 are the hardirq disable count (max # of hardirq disable: 256)
> > + * - bits 24-27 are the hardirq count (max # of hardirqs: 16)
> > * - bit 28 is the NMI flag (no nesting count, tracked separately)
> > *
> > * The hardirq count could in theory be the same as the number of
> > @@ -30,29 +32,34 @@
> > *
> > * PREEMPT_MASK: 0x000000ff
> > * SOFTIRQ_MASK: 0x0000ff00
> > - * HARDIRQ_MASK: 0x000f0000
> > + * HARDIRQ_DISABLE_MASK: 0x00ff0000
> > + * HARDIRQ_MASK: 0x0f000000
> > * NMI_MASK: 0x10000000
> > * PREEMPT_NEED_RESCHED: 0x80000000
> > */
> > #define PREEMPT_BITS 8
> > #define SOFTIRQ_BITS 8
> > +#define HARDIRQ_DISABLE_BITS 8
> > #define HARDIRQ_BITS 4
> > #define NMI_BITS 1
> >
> > #define PREEMPT_SHIFT 0
> > #define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS)
> > -#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS)
> > +#define HARDIRQ_DISABLE_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS)
> > +#define HARDIRQ_SHIFT (HARDIRQ_DISABLE_SHIFT + HARDIRQ_DISABLE_BITS)
> > #define NMI_SHIFT (HARDIRQ_SHIFT + HARDIRQ_BITS)
> >
> > #define __IRQ_MASK(x) ((1UL << (x))-1)
> >
> > #define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT)
> > #define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT)
> > +#define HARDIRQ_DISABLE_MASK (__IRQ_MASK(SOFTIRQ_BITS) << HARDIRQ_DISABLE_SHIFT)
>
> Should this be HARDIRQ_DISABLE_BITS rather than SOFTIRQ_BITS ?
>

Good catch! Yes, it' should be HARDIRQ_DISABLE_BITS. Thank you!

Regards,
Boqun

>
> Best regards,
> Andreas Hindborg
>
>