From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com,
andy@kernel.org, robh@kernel.org, conor+dt@kernel.org,
krzk+dt@kernel.org, linux-iio@vger.kernel.org, s32@nxp.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com
Subject: Re: [PATCH v5 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms
Date: Thu, 30 Oct 2025 11:28:08 +0200 [thread overview]
Message-ID: <aQMvqHGN7r6babgw@smile.fi.intel.com> (raw)
In-Reply-To: <050f96d5-e60c-4b33-b6d2-24fb3925e378@linaro.org>
On Thu, Oct 30, 2025 at 09:27:21AM +0100, Daniel Lezcano wrote:
> On 10/18/25 22:12, Andy Shevchenko wrote:
> > On Fri, Oct 17, 2025 at 06:42:38PM +0200, Daniel Lezcano wrote:
...
> > > +#include <linux/circ_buf.h>
> >
> > Why not kfifo?
>
> I'm sorry but I don't get your comment.
>
> Do you mean why not use kfifo.h or use kfifo API and change all the code
> using the circ_buf by the kfifo ?
Yes, I mean why use circ_buf API and not kfifo API.
...
> > > +#define NXP_SAR_ADC_IIO_BUFF_SZ (NXP_SAR_ADC_NR_CHANNELS + (sizeof(u64) / sizeof(u16)))
> >
> > Hmm... Don't we have some macros so we can avoid this kind of hard coding?
>
> I don't find such a macro, do you have a pointer ?
If I got the use case correctly, I was thinking of IIO_DECLARE_BUFFER_WITH_TS().
...
> > > + ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk)) * 80U);
> >
> > Do you need those 'U':s? clk_get_rate() already returns unsigned value of the
> > same or higher rank than int. No?
>
> May be not needed, but harmless. I can remove them if you want
I think using them in cases that have no side-effects are not needed.
...
> > > + dma_samples = (u32 *)dma_buf->buf;
> >
> > Is it aligned properly for this type of casting?
>
> TBH, I don't know the answer :/
>
> How can I check that ?
Is buf defined as a pointer to u32 / int or bigger? or is it just byte buffer?
If the latter, how does the address of it being formed? Does it come from a heap
(memory allocator)? If yes, we are fine, as this is usually the case for all
(k)malloc'ed memory.
...
> > > + dmaengine_tx_status(info->dma_chan, info->cookie, &state);
> >
> > No return value check?
>
> The return value is not necessary here because the caller of the callback
> will check with dma_submit_error() in case of error which covers the
> DMA_ERROR case and the other cases are not useful because the residue is
> taken into account right after.
In some cases it might return DMA_PAUSE (and actually this is the correct way
to get residue, one needs to pause the channel to read it, otherwise it will
give outdated / incorrect information).
> It could be written differently with the DMA_COMPLETE check but the result
> will be the same. I prefer to keep the current implementation which has been
> tested.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2025-10-30 9:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 16:42 [PATCH v5 0/2] NXP SAR ADC IIO driver for s32g2/3 platforms Daniel Lezcano
2025-10-17 16:42 ` [PATCH v5 1/2] dt-bindings: iio: adc: Add the NXP SAR ADC " Daniel Lezcano
2025-10-17 16:42 ` [PATCH v5 2/2] iio: adc: Add the NXP SAR ADC support for the " Daniel Lezcano
2025-10-18 20:12 ` Andy Shevchenko
2025-10-30 8:27 ` Daniel Lezcano
2025-10-30 9:28 ` Andy Shevchenko [this message]
2025-10-31 8:03 ` Daniel Lezcano
2025-10-31 11:32 ` Daniel Lezcano
2025-10-31 12:45 ` Andy Shevchenko
2025-11-07 11:36 ` Daniel Lezcano
2025-11-18 14:20 ` Andy Shevchenko
2025-11-18 13:57 ` Daniel Lezcano
2025-11-18 14:22 ` Andy Shevchenko
2025-10-19 8:42 ` Jonathan Cameron
2025-11-07 11:15 ` Vinod Koul
2025-11-09 12:52 ` Jonathan Cameron
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