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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 02:00:20.2920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5faea740-ca67-428d-37a3-08de18213f10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8251 On Mon, Oct 20, 2025 at 03:43:53PM -0700, Jacob Pan wrote: > From: Alexander Grest > > The SMMU CMDQ lock is highly contentious when there are multiple CPUs > issuing commands on an architecture with small queue sizes e.g 256 > entries. As Robin pointed out that 256 entry itself is not quite normal, the justification here might still not be very convincing.. I'd suggest to avoid saying "an architecture with a small queue sizes, but to focus on the issue itself -- potential starvation. "256-entry" can be used a testing setup to reproduce the issue. > The lock has the following states: > - 0: Unlocked > - >0: Shared lock held with count > - INT_MIN+N: Exclusive lock held, where N is the # of shared waiters > - INT_MIN: Exclusive lock held, no shared waiters > > When multiple CPUs are polling for space in the queue, they attempt to > grab the exclusive lock to update the cons pointer from the hardware. If > they fail to get the lock, they will spin until either the cons pointer > is updated by another CPU. > > The current code allows the possibility of shared lock starvation > if there is a constant stream of CPUs trying to grab the exclusive lock. > This leads to severe latency issues and soft lockups. It'd be nicer to have a graph to show how the starvation might happen due to a race: CPU0 (exclusive) | CPU1 (shared) | CPU2 (exclusive) | `cmdq->lock` -------------------------------------------------------------------------- trylock() //takes | | | 0 | shared_lock() | | INT_MIN | fetch_inc() | | INT_MIN | no return | | INT_MIN + 1 | spins // VAL >= 0 | | INT_MIN + 1 unlock() | spins... | | INT_MIN + 1 set_release(0) | spins... | | 0 <-- BUG? (done) | (sees 0) | trylock() // takes | 0 | *exits loop* | cmpxchg(0, INT_MIN) | 0 | | *cuts in* | INT_MIN | cmpxchg(0, 1) | | INT_MIN | fails // != 0 | | INT_MIN | spins // VAL >= 0 | | INT_MIN | *starved* | | INT_MIN And point it out that it should have reserved the "+1" from CPU1 instead of nuking the entire cmdq->lock to 0. > In a staged test where 32 CPUs issue SVA invalidations simultaneously on > a system with a 256 entry queue, the madvise (MADV_DONTNEED) latency > dropped by 50% with this patch and without soft lockups. This might not be very useful per Robin's remarks. I'd drop it. > Reviewed-by: Mostafa Saleh > Signed-off-by: Alexander Grest > Signed-off-by: Jacob Pan Reviewed-by: Nicolin Chen > @@ -500,9 +506,14 @@ static bool arm_smmu_cmdq_shared_tryunlock(struct arm_smmu_cmdq *cmdq) > __ret; \ > }) > > +/* > + * Only clear the sign bit when releasing the exclusive lock this will > + * allow any shared_lock() waiters to proceed without the possibility > + * of entering the exclusive lock in a tight loop. > + */ > #define arm_smmu_cmdq_exclusive_unlock_irqrestore(cmdq, flags) \ > ({ \ > - atomic_set_release(&cmdq->lock, 0); \ > + atomic_fetch_and_release(~INT_MIN, &cmdq->lock); \ Align the tailing spacing with other lines please. Nicolin