[kvm-unit-tests patch v3 8/8] x86: pmu_pebs: Support to validate timed PEBS record on GNR/SRF

Dapeng Mi
2025-09-03T06:47:49Z

On Intel GNR/SRF platform, timed PEBS is introduced. Timed PEBS adds
a new "retired latency" field in basic info group to show the timing
info. IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to
indicate whether timed PEBS is supported.

After introducing timed PEBS, the PEBS record format field shrinks to
bits[31:0] and the bits[47:32] is used to record retired latency.

Thus shrink the record format to bits[31:0] accordingly and avoid the
retired latency field is recognized a part of record format to compare
and cause failure on GNR/SRF.

Please find detailed information about timed PEBS in section 8.4.1
"Timed Processor Event Based Sampling" of "Intel Architecture
Instruction Set Extensions and Future Features".

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
---
lib/x86/pmu.h | 6 ++++++
x86/pmu_pebs.c | 8 +++++---
2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h
index c7dc68c1..86a7a05f 100644
--- a/lib/x86/pmu.h
+++ b/lib/x86/pmu.h
@@ -20,6 +20,7 @@
#define PMU_CAP_LBR_FMT 0x3f
#define PMU_CAP_FW_WRITES (1ULL << 13)
#define PMU_CAP_PEBS_BASELINE (1ULL << 14)
+#define PMU_CAP_PEBS_TIMING_INFO (1ULL << 17)
#define PERF_CAP_PEBS_FORMAT 0xf00

#define EVNSEL_EVENT_SHIFT 0
@@ -188,4 +189,9 @@ static inline bool pmu_has_pebs_baseline(void)
return pmu.perf_cap & PMU_CAP_PEBS_BASELINE;
}

+static inline bool pmu_has_pebs_timing_info(void)
+{
+ return pmu.perf_cap & PMU_CAP_PEBS_TIMING_INFO;
+}
+
#endif /* _X86_PMU_H_ */
diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c
index 2848cc1e..bc37e8e3 100644
--- a/x86/pmu_pebs.c
+++ b/x86/pmu_pebs.c
@@ -277,6 +277,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive
unsigned int count = 0;
bool expected, pebs_idx_match, pebs_size_match, data_cfg_match;
void *cur_record;
+ u64 format_mask;

expected = (ds->pebs_index == ds->pebs_buffer_base) && !pebs_rec->format_size;
if (!(rdmsr(MSR_CORE_PERF_GLOBAL_STATUS) & GLOBAL_STATUS_BUFFER_OVF)) {
@@ -289,6 +290,8 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive
return;
}

+ /* Record format shrinks to bits[31:0] after timed PEBS is introduced. */
+ format_mask = pmu_has_pebs_timing_info() ? GENMASK_ULL(31, 0) : GENMASK_ULL(47, 0);
expected = ds->pebs_index >= ds->pebs_interrupt_threshold;
cur_record = (void *)pebs_buffer;
do {
@@ -296,8 +299,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive
pebs_record_size = pebs_rec->format_size >> RECORD_SIZE_OFFSET;
pebs_idx_match = pebs_rec->applicable_counters & bitmask;
pebs_size_match = pebs_record_size == get_pebs_record_size(pebs_data_cfg, use_adaptive);
- data_cfg_match = (pebs_rec->format_size & GENMASK_ULL(47, 0)) ==
- (use_adaptive ? pebs_data_cfg : 0);
+ data_cfg_match = (pebs_rec->format_size & format_mask) == (use_adaptive ? pebs_data_cfg : 0);
expected = pebs_idx_match && pebs_size_match && data_cfg_match;
report(expected,
"PEBS record (written seq %d) is verified (including size, counters and cfg).", count);
@@ -327,7 +329,7 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive
pebs_record_size, get_pebs_record_size(pebs_data_cfg, use_adaptive));
if (!data_cfg_match)
printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with the effective MSR_PEBS_DATA_CFG (0x%lx).\n",
- pebs_rec->format_size & 0xffffffffffff, use_adaptive ? pebs_data_cfg : 0);
+ pebs_rec->format_size & format_mask, use_adaptive ? pebs_data_cfg : 0);
}
}

--
2.34.1