From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Jonas Gorski <jonas.gorski@gmail.com>
Cc: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>,
Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/2] spi: microchip-core: use XOR instead of ANDNOT to simplify the logic
Date: Sat, 29 Nov 2025 10:19:00 +0200 [thread overview]
Message-ID: <aSqsdKpJ7CDd6jJn@smile.fi.intel.com> (raw)
In-Reply-To: <CAOiHx==y-4Jjckr-KnwdmJhi=TR9_wzcHvNo8GAeUmJ43Y_bHw@mail.gmail.com>
On Fri, Nov 28, 2025 at 08:30:43PM +0100, Jonas Gorski wrote:
> On Fri, Nov 28, 2025 at 7:56 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
...
> > - if (spi->mode & SPI_MODE_X_MASK & ~spi->controller->mode_bits) {
> > + if ((spi->mode ^ spi->controller->mode_bits) & SPI_MODE_X_MASK) {
>
> This changes the behavior: if a bit isn't set in spi->mode that is set
> in mode_bits, it would have been previously accepted, now it's
> refused. E.g. controller has (SPI_CPOL | SPI_CPHA), device only
> SPI_CPOL. 0x1 & 0x3 & ~0x3 => 0, vs (0x1 ^ 0x3) & 0x3 => 0x2
>
> If this is the actually intended behavior here, it is a fix and should
> carry a Fixes tag (the message below implies that).
Yeah, yesterday I was thinking about the same and I was confused by the logic
behind. As far as I understood the comments regarding mode provided by DT is
that the mode is configured in IP and may not be changed. And you are right
about the fix, but let's wait for Microchip to elaborate on the expected
behaviour.
> > dev_err(&spi->dev, "incompatible CPOL/CPHA, must match controller's Motorola mode\n");
> > return -EINVAL;
> > }
Thanks for the review!
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2025-11-29 8:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-28 18:52 [PATCH v4 0/2] spi: microchip-core: Code improvements (part 2) Andy Shevchenko
2025-11-28 18:52 ` [PATCH v4 1/2] spi: microchip-core: Refactor FIFO read and write handlers Andy Shevchenko
2025-11-28 18:52 ` [PATCH v4 2/2] spi: microchip-core: use XOR instead of ANDNOT to simplify the logic Andy Shevchenko
2025-11-28 19:30 ` Jonas Gorski
2025-11-29 8:19 ` Andy Shevchenko [this message]
2025-12-01 16:08 ` Conor Dooley
2025-12-01 17:57 ` Andy Shevchenko
2026-01-08 13:00 ` Prajna Rajendra Kumar
2026-01-08 17:53 ` Andy Shevchenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aSqsdKpJ7CDd6jJn@smile.fi.intel.com \
--to=andriy.shevchenko@linux.intel.com \
--cc=broonie@kernel.org \
--cc=jonas.gorski@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=prajna.rajendrakumar@microchip.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox