[PATCH rc v2 0/4] iommu/arm-smmu-v3: Fix hitless STE update in nesting cases

Nicolin Chen
2025-12-07T20:49:59Z

Occasional C_BAD_STE errors were observed in nesting setups where a device
attached to a nested bypass/identity domain enables PASID.

This occurred when the physical STE was updated from S2-only mode to S1+S2
nesting mode, but the update failed to use the hitless routine that it was
supposed to use. Instead, it cleared STE.V bit to load the CD table, while
the default substream was still actively performing DMA.

It was later found that the diff algorithm in arm_smmu_entry_qword_diff()
enforced an additional critical word due to misaligned MEV and EATS fields
between S2-only and S1+S2 modes.

Both fields are either well-managed or non-critical, so move them to the
"ignored" list to relax the qword diff algorithm.

Additionally, add KUnit test coverage for these nesting STE cases.

This is on Github:
https://github.com/nicolinc/iommufd/commits/smmuv3_ste_fixes/

A host kernel must apply this to fix the bug.

Changelog
v2:
* Fix kunit tests
* Update commit message
* Keep MEV/EATS in used list by masking them away using ignored_bits
v1:
https://lore.kernel.org/all/cover.1764982046.git.nicolinc@nvidia.com/

Jason Gunthorpe (3):
iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence
iommu/arm-smmu-v3: Ignore STE MEV when computing the update sequence
iommu/arm-smmu-v3: Ignore STE EATS when computing the update sequence

Nicolin Chen (1):
iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 80 ++++++++++++++++++-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 43 ++++++++--
3 files changed, 117 insertions(+), 8 deletions(-)

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2.43.0