Re: [PATCH rc v2 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage

Nicolin Chen
2025-12-09T21:05:19Z

On Mon, Dec 08, 2025 at 11:43:41AM +0800, Shuai Xue wrote:
> Hi, Nicolin,
>
> Nit. Instead of duplicating this code, we can leverage the existing
> arm_smmu_test_make_cdtable_ste() helper here.

Thanks for the review. I squashed the following changes:

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
index 1672e75ebffc2..197b8b55fe7a2 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
@@ -33,8 +33,12 @@ static struct mm_struct sva_mm = {
enum arm_smmu_test_master_feat {
ARM_SMMU_MASTER_TEST_ATS = BIT(0),
ARM_SMMU_MASTER_TEST_STALL = BIT(1),
+ ARM_SMMU_MASTER_TEST_NESTED = BIT(2),
};

+static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste,
+ enum arm_smmu_test_master_feat feat);
+
static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry,
const __le64 *used_bits,
const __le64 *target,
@@ -198,6 +202,17 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_smmu_ste *ste,
};

arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss);
+ if (feat & ARM_SMMU_MASTER_TEST_NESTED) {
+ struct arm_smmu_ste s2ste;
+ int i;
+
+ arm_smmu_test_make_s2_ste(&s2ste, ARM_SMMU_MASTER_TEST_ATS);
+ ste->data[0] |= cpu_to_le64(
+ FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED));
+ ste->data[1] |= cpu_to_le64(STRTAB_STE_1_MEV);
+ for (i = 2; i < NUM_ENTRY_QWORDS; i++)
+ ste->data[i] = s2ste.data[i];
+ }
}

static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test)
@@ -555,46 +570,17 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(struct kunit *test)
NUM_EXPECTED_SYNCS(3));
}

-static void arm_smmu_test_make_nested_cdtable_ste(
- struct arm_smmu_ste *ste, unsigned int s1dss, const dma_addr_t dma_addr,
- enum arm_smmu_test_master_feat feat)
-{
- bool stall_enabled = feat & ARM_SMMU_MASTER_TEST_STALL;
- bool ats_enabled = feat & ARM_SMMU_MASTER_TEST_ATS;
- struct arm_smmu_ste s1ste;
-
- struct arm_smmu_master master = {
- .ats_enabled = ats_enabled,
- .cd_table.cdtab_dma = dma_addr,
- .cd_table.s1cdmax = 0xFF,
- .cd_table.s1fmt = STRTAB_STE_0_S1FMT_64K_L2,
- .smmu = &smmu,
- .stall_enabled = stall_enabled,
- };
-
- arm_smmu_test_make_s2_ste(ste, ARM_SMMU_MASTER_TEST_ATS);
- arm_smmu_make_cdtable_ste(&s1ste, &master, ats_enabled, s1dss);
-
- ste->data[0] = cpu_to_le64(
- STRTAB_STE_0_V |
- FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED));
- ste->data[0] |= s1ste.data[0] & ~cpu_to_le64(STRTAB_STE_0_CFG);
- ste->data[1] |= s1ste.data[1];
- /* Merge events for DoS mitigations on eventq */
- ste->data[1] |= cpu_to_le64(STRTAB_STE_1_MEV);
-}
-
static void
arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *test)
{
struct arm_smmu_ste s1_ste;
struct arm_smmu_ste s2_ste;

- arm_smmu_test_make_nested_cdtable_ste(&s1_ste,
- STRTAB_STE_1_S1DSS_BYPASS,
- fake_cdtab_dma_addr,
- ARM_SMMU_MASTER_TEST_ATS);
+ arm_smmu_test_make_cdtable_ste(
+ &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr,
+ ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED);
arm_smmu_test_make_s2_ste(&s2_ste, 0);
+ /* Expect an additional sync to unset ignored bits: EATS and MEV */
arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste,
NUM_EXPECTED_SYNCS(3));
}
@@ -605,10 +591,9 @@ arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *test)
struct arm_smmu_ste s1_ste;
struct arm_smmu_ste s2_ste;

- arm_smmu_test_make_nested_cdtable_ste(&s1_ste,
- STRTAB_STE_1_S1DSS_BYPASS,
- fake_cdtab_dma_addr,
- ARM_SMMU_MASTER_TEST_ATS);
+ arm_smmu_test_make_cdtable_ste(
+ &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr,
+ ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED);
arm_smmu_test_make_s2_ste(&s2_ste, 0);
arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste,
NUM_EXPECTED_SYNCS(2));