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[34.140.140.54]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a8f3352a0sm14417635e9.0.2025.12.12.08.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Dec 2025 08:15:36 -0800 (PST) Date: Fri, 12 Dec 2025 16:15:33 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jean-philippe@linaro.org, praan@google.com, danielmentz@google.com, mark.rutland@arm.com, qperret@google.com, tabba@google.com Subject: Re: [PATCH v5 27/27] iommu/arm-smmu-v3-kvm: Enable nesting Message-ID: References: <20251117184815.1027271-1-smostafa@google.com> <20251117184815.1027271-28-smostafa@google.com> <20251128171252.GF812105@ziepe.ca> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251128171252.GF812105@ziepe.ca> On Fri, Nov 28, 2025 at 01:12:52PM -0400, Jason Gunthorpe wrote: > On Mon, Nov 17, 2025 at 06:48:14PM +0000, Mostafa Saleh wrote: > > @@ -441,8 +490,32 @@ static void smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool > > hyp_ste_ptr = smmu_get_ste_ptr(smmu, sid, hyp_ste_base); > > } > > > > - smmu_copy_from_host(smmu, hyp_ste_ptr->data, host_ste_ptr->data, > > + smmu_copy_from_host(smmu, target.data, host_ste_ptr->data, > > STRTAB_STE_DWORDS << 3); > > + /* > > + * Typically, STE update is done as the following > > + * 1- Write last 7 dwords, while STE is invalid > > + * 2- CFGI > > + * 3- Write first dword, making STE valid > > + * 4- CFGI > > + * As the SMMU MUST at least load 64 bits atomically > > + * that gurantees that there is no race between writing > > + * the STE and the CFGI where the SMMU observes parts > > + * of the STE. > > + * In the shadow we update the STE to enable nested translation, > > + * which requires updating first 4 dwords. > > + * That is only done if the STE is valid and not in abort. > > + * Which means it happens at step 4) > > + * So we need to also write the last 7 dwords and send CFGI > > + * before writing the first dword. > > + * There is no need for last CFGI as it's done next. > > + */ > > This really should share the main driver logic to do STE writes in the > right order and try to avoid making it non-valid if not necessary. > > This will not properly support all the real-world kernel flows around > PASID with such a simplistic implementation. > > I see, would it be OK to keep it as this simple now and add this later, as this is still early support? as I want to keep this series minimal. I plan to have another seires with some improvements and optimizations, mostly about page tables (using block mappings) and I can include such optimization, specially that the new hitless STE stuff is relatively recent in the main driver. Thanks, Mostafa > Json