From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5819B3B8D57 for ; Mon, 15 Dec 2025 13:55:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765806934; cv=none; b=tYqRYP9sVwQXRwTPjHP8Tu9I/7NTkU+EyI3gUS9mSATeeyJUAE+UceY7biY121i/6MvACdzSruOCYo8dv2qtAmZXKrn/Sh6sm0dbVh0hDws/jJY6GaU5pbvwHmpPRjbani5dzgNHcLPm0enl/StHLZEs2OUnHQXhUGISbyISbKk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765806934; c=relaxed/simple; bh=BeEPXRzY5Y/ATHtZVbLsiDrSsgiAh29XaKN2Ga4NzOk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Fh+inTfEH7DMYAUYmZxz5o01njfTVyG837WG8fzm9oRe/lvFMlIHTRf0+2IGhZervcfTa5lzoq+2eHpw8v4+UUeAKJ4t+qlNk34U2+Bnvxw4ghu6AIT/g1jOZ0QjiMWNLb2qeckr9JnUUqdPkbsuzy97+720mbbivc3JSJgUKBY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rDZQO3KP; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=vRff/wH4; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rDZQO3KP"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="vRff/wH4" Date: Mon, 15 Dec 2025 14:55:27 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1765806930; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=IroafU4+6Qt+Kjc1H6W95Dy9I0YmrzOb1vqFVvWTHo0=; b=rDZQO3KPa3UtRcQWBchW2VJaHdF84/y/lXDiXYkNOAAp2YrAiIlaR/gDtLH0DHCqIyYgHp 3RBLx25f/ROzbPNFkwlEIiSxfBNtZN6GHTfUVjXMwYAvxTORpmwYAF5Pa1L6F/I7r5YhR0 AYrWMUwWyGoDVvsQwPU1qv6cBPF4jqZstGFW6I1uGvqpwFt9f9MRoE14uJoGD5kx+qiRac 5z6e3AMdTeveVGXmfd9GejcwSnZqGKBgHNpl1kP550/PN7vk5qN3PxOzuooKcaC6j9Ccdr kYH907FadrkRfXi2l5eBhZU96nioM2p6zy1jp/c+B4CIdkU8xu/B8BIcQzgUKA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1765806930; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=IroafU4+6Qt+Kjc1H6W95Dy9I0YmrzOb1vqFVvWTHo0=; b=vRff/wH4zwsDp/xp/UdhQ8lNtHtJEulw9gV5bccmIMvJw7apiJ8uBO6nSLqsuOcVrfyL1q 8hbEEs9HZuZI42Bw== From: "Ahmed S. Darwish" To: Brian Gerst Cc: Ingo Molnar , linux-kernel@vger.kernel.org, Andrew Cooper , Ard Biesheuvel , Arnd Bergmann , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , Thomas Gleixner Subject: Re: [PATCH -v3 0/15] x86: Remove support for TSC-less and CX8-less CPUs Message-ID: References: <20251214084710.3606385-1-mingo@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi, On Sun, 14 Dec 2025, Brian Gerst wrote: > > Does this also eliminate all processors that do not support CPUID? > If it does, then we can also remove X86_FEATURE_CPUID from word 3: --- linux.orig/arch/x86/include/asm/cpufeatures.h +++ linux/arch/x86/include/asm/cpufeatures.h @@ -94,3 +94,3 @@ #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* "nonstop_tsc" TSC does not stop in C states */ -#define X86_FEATURE_CPUID ( 3*32+25) /* "cpuid" CPU has CPUID instruction itself */ +/* Reserved ( 3*32+25) */ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* "extd_apicid" Extended APICID (8 bits) */ plus its call sites. Thanks, Ahmed