[PATCH v2 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs

Dan Carpenter
2025-12-15T14:41:58Z

The NXP S32 SoCs have a GPR region which is used by a variety of
drivers. Some examples of the registers in this region are:

* DDR_PMU_IRQ
* GMAC0_PHY_INTF_SEL
* GMAC1_PHY_INTF_SEL
* PFE_EMACS_INTF_SEL
* PFE_COH_EN
* PFE_PWR_CTRL
* PFE_EMACS_GENCTRL1
* PFE_GENCTRL3

Use the syscon interface to access these registers.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v2: Use nxp,s32g2-gpr and nxp,s32g3-gpr instead of nxp,s32g-gpr

Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 55efb83b1495..694733aeb270 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -102,6 +102,8 @@ select:
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
+ - nxp,s32g2-gpr
+ - nxp,s32g3-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
@@ -212,6 +214,8 @@ properties:
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
+ - nxp,s32g2-gpr
+ - nxp,s32g3-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
--
2.51.0