Re: [PATCH v2 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon

Krzysztof Kozlowski
2025-12-17T08:37:05Z

On Mon, Dec 15, 2025 at 05:41:57PM +0300, Dan Carpenter wrote:
> The S32 chipsets have a GPR region which has a miscellaneous registers
> including the GMAC_0_CTRL_STS register. Originally, this code accessed
> that register in a sort of ad-hoc way, but it's cleaner to use a
> syscon interface to access these registers.
>
> We still need to maintain the old method of accessing the GMAC register
> but using a syscon will let us access other registers more cleanly.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> v2: Add the vendor prefix to the phandle
> Fix the documentation
>
> .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..a65036806d60 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> @@ -32,6 +32,15 @@ properties:
> - description: Main GMAC registers
> - description: GMAC PHY mode control register
>
> + nxp,phy-sel:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - description: phandle to the GPR syscon node
> + - description: offset of PHY selection register
> + description:
> + This is a phandle/offset pair. The phandle points to the
> + GPR region and the offset is the GMAC_0_CTRL_STS register.

Do not repeat description twice. The GMAC_0_CTRL_STS should be explained
in description of individual item. This description should only say what
is the purpose of it, why the hardware needs to poke in other devices.

Best regards,
Krzysztof