Re: [PATCH v2 0/4] s32g: Use a syscon for GPR

Frank Li
2025-12-17T19:54:05Z

On Tue, Dec 16, 2025 at 09:30:08PM +0300, Dan Carpenter wrote:
> On Tue, Dec 16, 2025 at 09:42:06AM -0500, Frank Li wrote:
> > > >
> > > > Why not implement standard phy interface,
> > > > phy_set_mode_ext(PHY_MODE_ETHERNET, RGMII);
> > > >
> > > > For example: drivers/pci/controller/dwc/pci-imx6.c
> > > >
> > > > In legency platform, it use syscon to set some registers. It becomes mess
> > > > when more platform added. And it becomes hard to convert because avoid
> > > > break compatibltiy now.
> > > >
> > > > It doesn't become worse since new platforms switched to use standard
> > > > inteface, (phy, reset ...).
> > > >
> > >
> > > This happens below that layer, this is just saying where the registers
> > > are found. The GMAC_0_CTRL_STS is just one register in the GPR region,
> > > most of the others are unrelated to PHY.
> >
> > The other register should work as other function's providor with mfd.
> >
>
> Syscons are a really standard way to do register accesses.

It is quite like back door. Many clock/reset also use phandle to node to
controller by raw register read/write.

> The
> pci-imx6.c driver you mentioned earlier does it that way...

It is not preferred when we tried to add new one. Give me some time to look
for original threads.

> The only
> thing which my code does differently is I put the offset into the
> phandle, but that's not so unusual and it's arguably a cleaner way
> because now both the base address and offset are in the same file.

It is not big deal about offset. The key is if use phande to direct access
other module's register.

Frank
>
> regards,
> dan carpenter
>