Re: [PATCH v2 0/4] s32g: Use a syscon for GPR

Dan Carpenter
2025-12-15T20:11:09Z

On Mon, Dec 15, 2025 at 02:28:43PM -0500, Frank Li wrote:
> On Mon, Dec 15, 2025 at 09:33:54PM +0300, Dan Carpenter wrote:
> > On Mon, Dec 15, 2025 at 10:56:49AM -0500, Frank Li wrote:
> > > On Mon, Dec 15, 2025 at 05:41:43PM +0300, Dan Carpenter wrote:
> > > > The s32g devices have a GPR register region which holds a number of
> > > > miscellaneous registers. Currently only the stmmac/dwmac-s32.c uses
> > > > anything from there and we just add a line to the device tree to
> > > > access that GMAC_0_CTRL_STS register:
> > > >
> > > > reg = <0x4033c000 0x2000>, /* gmac IP */
> > > > <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
> > > >
> > > > We still have to maintain backwards compatibility to this format,
> > > > of course, but it would be better to access these through a syscon.
> > > > First of all, putting all the registers together is more organized
> > > > and shows how the hardware actually is implemented. Secondly, in
> > > > some versions of this chipset those registers can only be accessed
> > > > via SCMI, if the registers aren't grouped together each driver will
> > > > have to create a whole lot of if then statements to access it via
> > > > IOMEM or via SCMI,
> > >
> > > Does SCMI work as regmap? syscon look likes simple, but missed abstract
> > > in overall.
> > >
> >
> > The SCMI part of this is pretty complicated and needs discussion. It
> > might be that it requires a vendor extension. Right now, the out of
> > tree code uses a nvmem vendor extension but that probably won't get
> > merged upstream.
> >
> > But in theory, it's fairly simple, you can write a regmap driver and
> > register it as a syscon and everything that was accessing nxp,phy-sel
> > accesses the same register but over SCMI.
>
> nxp,phy-sel is not standard API. Driver access raw register value. such
> as write 1 to offset 0x100.
>
> After change to SCMI, which may mapped to difference command. Even change
> to other SOC, value and offset also need be changed. It is not standilzed
> as what you expected.

We're writing to an offset in a syscon. Right now the device tree
says that the syscon is an MMIO syscon. But for SCMI devices we
would point the phandle to a custom syscon. The phandle and the offset
would stay the same, but how the syscon is implemented would change.

>
> >
> > > You still use regmap by use MMIO. /* GMAC_0_CTRL_STS */
> > >
> > > regmap = devm_regmap_init_mmio(dev, sts_offset, &regmap_config);
> > >
> >
> > You can use have an MMIO syscon, or you can create a custom driver
> > and register it as a syscon using of_syscon_register_regmap().
>
> My means is that it is not necessary to create nxp,phy-sel, especially
> there already have <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
>

Right now the out of tree dwmac-s32cc.c driver does something like
this:

89 if (gmac->use_nvmem) {
90 ret = write_nvmem_cell(gmac->dev, "gmac_phy_intf_sel", intf_sel);
91 if (ret)
92 return ret;
93 } else {
94 writel(intf_sel, gmac->ctrl_sts);
95 }

Which is quite complicated, but with a syscon, then it's just:

regmap_write(gmac->sts_regmap, gmac->sts_offset, S32_PHY_INTF_SEL_RGMII);

Even without SCMI, the hardware has all these registers grouped together
it just feels cleaner to group them together in the device tree as well.

regards,
dan carpenter