From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 069222F12B3 for ; Thu, 18 Dec 2025 16:40:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766076037; cv=none; b=J/FAeUC4gV9IAsu21HzNo8jYvfCWMXpq6Ui8Yyc++NFmRlqSr8Xul7I8l8m0qmOABSRQeIDlK0oqhtHE79cwfPZokWiTk1610cdvwf/eJ2wU64s5RJEKmSrEfjXlXrEl4eeNmjQ/stJQSKCB1Mw3Gxe2oW0djz3ifvucJpiS2oE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766076037; c=relaxed/simple; bh=awiaqiCZDp63bNwX+H3yrYRLubLpus6xlU3QTONpaMo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=TGAzEkkKz6IAbPwAbUuyvuCFDBFemjRe8NMGtM4/zDbxALR4JFRYcKSERHYOmWTUn9iF5vGiIsZqf2+ypDwtUzw9DQsz4W5BjBVvtrkRPXTmyY/123/JmKTvIrCXwZlFbHtFFW06rrOjx8pq6TIg9S6pQm5EZYuxuNs02KDW9Ws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=CvzABq22; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="CvzABq22" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4779a4fb9bfso66055e9.0 for ; Thu, 18 Dec 2025 08:40:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1766076034; x=1766680834; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=wVStRMWg0rfP2fEwAd11bQqAyXNa+0/i9rP/tVPAzuw=; b=CvzABq22tYBSIz9H9nCLvANo9aw654Yob7rc9KPi6ONQZup6Lsx+tY/OQsb4KXKwL4 7qLXChX7KH0NEEOqQlU5tO7J7RY2IR3DxlnKbHjSEOIP2/derP3JrzEsGCeyLOGmIQXw tl2XD8PcsGAZTQdyEFHiqLtz5btjzGepPRzFRPicY1PM47BpDL/QlfTjyP1n0F/nxgir EcQu5VipRVFdWaKG4CZvz+lM2gWG+twb/PY/+VR9GFvGHOY8SW+jsfY2dgZMg1C12vmq 6mbNBWwcRpgyNxMbF6+pdtmYcWCQ7BZ+nsinLmmhIgbywnMluZUaXM3NMMcpOFdO9gz0 XBhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766076034; x=1766680834; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wVStRMWg0rfP2fEwAd11bQqAyXNa+0/i9rP/tVPAzuw=; b=g23HWGVmHJOnt+2iiI7EK0CSjchIKt9FdEqfrrJBkeIH7Tbb0OiSkO1BvO7/RK48Lj RRE3DWDLqaXg86mmAFRwdCfjeydENAxECUGSz6rp/+b3iyeDuhOSGbAQm1ZdZkraQnlk CtR5Qf9z29lO2PG9hTcrvLnvX5yn5jLxaxAZX/GeT4dUQz/k8DDVQRgsiBUpD65Hmg46 +WEOol1hpX2zKZcy+orA9cO5B3AebcEAHHd3CRMWJ6Yxt4hnLP5YfrAGr2ByvWefOigM a9iGysPYOudPUo2xic33jpKcx1WdPJKuZ0j9bSvmfeBUw7culFrzGpuYdDhDr9MqPHf0 XP7Q== X-Forwarded-Encrypted: i=1; AJvYcCUdX21q/eRj27v0UFJ1HHfJ4u9K/xZN4yZ8yMw3ZnUu4Sqs7rLUCGgHY+9U6fKHVdmGYqSA//deZ7Gmzjk=@vger.kernel.org X-Gm-Message-State: AOJu0Ywx0at7NmRzBJrc3HTKQZQ2tZVgR+n6GJZjUNrirDHyYsqjVJPs cdq2d51bwhxQGaTUFUDYrp6ZeBrZEVDfXF7Yr/BJKo0mLb36hHKvgFWYWLTBN0Owgw== X-Gm-Gg: AY/fxX76I8fYRHK/LxJJHKBKiZy++FlgmlbYVuEclwKtzY60dct1ObPoQ80vUnqd+Rw Zt/6WPm8b0TUVyCUKvc7S4LxZmzIl76gg+GMq3xSbO3o3xIt/zXDpXgELOyc4Qt3Ej3zGnj+r26 xoRqzITGYosTctAcE696Ed002+RUrY7nTT2GI53UgkBjpox4Gbl6wJ3FnJUZCbHNby3s5xqRxsO HHXIC/oHajeI8epnVNrMSxBfNJYJX7N160zoxl8umAh3nG3xYepAzNSPT5A14z6hGFValq+KcdB Gh/P6JV/BrPCR930KVcWFuiWXnNMu2UElNfXabX+gh7fOIv5tY/ZQ296Q7nP1yPLFyKedhz/4tR a/1tfL/I7BumbKXogvONaVx/CZ06EQJZ8+epbOLsDsHOBdRcLxwiFNJmHPK7NVkHOO0K2FLlsWS kfevi2Un9gqw/a792NrOQHIFlVe3HX6ZY2VkqX+qmCuyfDRH3noqZq X-Google-Smtp-Source: AGHT+IEo5WDa5tT3Thb5LCrx68hS9Zizs1jUbVh5VWo2CFXMBk1R2s+dqf9FAll8MkOddqKisw01vg== X-Received: by 2002:a05:600c:686:b0:477:b358:c0cc with SMTP id 5b1f17b1804b1-47c010b90a8mr342415e9.17.1766076033956; Thu, 18 Dec 2025 08:40:33 -0800 (PST) Received: from google.com (171.85.155.104.bc.googleusercontent.com. [104.155.85.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432449987a4sm5776517f8f.31.2025.12.18.08.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 08:40:33 -0800 (PST) Date: Thu, 18 Dec 2025 16:40:30 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, skolothumtho@nvidia.com, praan@google.com, xueshuai@linux.alibaba.com Subject: Re: [PATCH rc v4 2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence Message-ID: References: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1765945258.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1765945258.git.nicolinc@nvidia.com> On Tue, Dec 16, 2025 at 08:26:00PM -0800, Nicolin Chen wrote: > From: Jason Gunthorpe > > Nested CD tables set the MEV bit to try to reduce multi-fault spamming on > the hypervisor. Since MEV is in STE word 1 this causes a breaking update > sequence that is not required and impacts real workloads. > > For the purposes of STE updates the value of MEV doesn't matter, if it is > set/cleared early or late it just results in a change to the fault reports > that must be supported by the kernel anyhow. The spec says: > > Note: Software must expect, and be able to deal with, coalesced fault > records even when MEV == 0. > > So mark STE MEV safe when computing the update sequence, to avoid creating > a breaking update. > > Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations") > Cc: stable@vger.kernel.org > Signed-off-by: Jason Gunthorpe > Reviewed-by: Shuai Xue > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) Reviewed-by: Mostafa Saleh Thanks, Mostafa > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 8dbf4ad5b51e..12a9669bcc83 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); > VISIBLE_IF_KUNIT > void arm_smmu_get_ste_update_safe(__le64 *safe_bits) > { > + /* > + * MEV does not meaningfully impact the operation of the HW, it only > + * changes how many fault events are generated, thus we can relax it > + * when computing the ordering. The spec notes the device can act like > + * MEV=1 anyhow: > + * > + * Note: Software must expect, and be able to deal with, coalesced > + * fault records even when MEV == 0. > + */ > + safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV); > } > EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe); > > -- > 2.43.0 >