[PATCH 0/2] drm/msm/dpu: Revert broken parts of the quad pipe support

[PATCH 0/2] drm/msm/dpu: Revert broken parts of the quad pipe support

[Abel Vesa]

There are quite a few reports off-list that, at least on Hamoa based
devices, there are some IOMMU faults and some abnormal artifacts on eDP.
These have been traced to the quad pipe support introduced in 6.19-rc1.

Meanwhile, Marijn reported some issues in some dual-DSI dual-DSC scenario.

Off-list discussion concluded into reverting these two commits to avoid
the described issues.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Abel Vesa (2):
      Revert "drm/msm/dpu: support plane splitting in quad-pipe case"
      Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case"

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         |  38 ++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |   8 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      |  29 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c        | 137 +++++++----------------
 7 files changed, 73 insertions(+), 145 deletions(-)
---
base-commit: cc3aa43b44bdb43dfbac0fcb51c56594a11338a8
change-id: 20251219-drm-msm-dpu-revert-quad-pipe-broken-7b249567917e

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH 1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case"

[Abel Vesa]

This reverts commit 5978864e34b66bdae4d7613834c03dd5d0a0c891.

At least on Hamoa based devices, there are IOMMU faults:

arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x00000000, fsynr=0x3d0023, cbfrsynra=0x1c00, cb=13
arm-smmu 15000000.iommu: FSR    = 00000402 [Format=2 TF], SID=0x1c00
arm-smmu 15000000.iommu: FSYNR0 = 003d0023 [S1CBNDX=61 PNU PLVL=3]

While on some of these devices, there are also all sorts of artifacts on eDP.

Reverting this fixes these issues.

Closes: https://lore.kernel.org/r/z75wnahrp7lrl5yhfdysr3np3qrs6xti2i4otkng4ex3blfgrx@xyiucge3xykb/
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  11 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 137 +++++++++---------------------
 3 files changed, 40 insertions(+), 110 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index c39f1908ea65..011946bbf5a2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1620,17 +1620,6 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
 	return 0;
 }
 
-/**
- * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline
- * @state: Pointer to drm crtc state object
- */
-unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state)
-{
-	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
-
-	return cstate->num_mixers;
-}
-
 #ifdef CONFIG_DEBUG_FS
 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 455073c7025b..2c83f1578fc3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -267,6 +267,4 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type(
 
 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event);
 
-unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state);
-
 #endif /* _DPU_CRTC_H_ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index d07a6ab6e7ee..9b7a8b46bfa9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -826,12 +826,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
 	struct dpu_sw_pipe_cfg *pipe_cfg;
 	struct dpu_sw_pipe_cfg *r_pipe_cfg;
-	struct dpu_sw_pipe_cfg init_pipe_cfg;
 	struct drm_rect fb_rect = { 0 };
-	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 	uint32_t max_linewidth;
-	u32 num_lm;
-	int stage_id, num_stages;
 
 	min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO);
 	max_scale = MAX_DOWNSCALE_RATIO << 16;
@@ -854,10 +850,13 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
 		return -EINVAL;
 	}
 
-	num_lm = dpu_crtc_get_num_lm(crtc_state);
-
+	/* move the assignment here, to ease handling to another pairs later */
+	pipe_cfg = &pstate->pipe_cfg[0];
+	r_pipe_cfg = &pstate->pipe_cfg[1];
 	/* state->src is 16.16, src_rect is not */
-	drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src);
+	drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
+
+	pipe_cfg->dst_rect = new_plane_state->dst;
 
 	fb_rect.x2 = new_plane_state->fb->width;
 	fb_rect.y2 = new_plane_state->fb->height;
@@ -882,94 +881,35 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
 
 	max_linewidth = pdpu->catalog->caps->max_linewidth;
 
-	drm_rect_rotate(&init_pipe_cfg.src_rect,
+	drm_rect_rotate(&pipe_cfg->src_rect,
 			new_plane_state->fb->width, new_plane_state->fb->height,
 			new_plane_state->rotation);
 
-	/*
-	 * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair
-	 * configs for left and right half screen in case of 4:4:2 topology.
-	 * But we may have 2 rect to split wide plane that exceeds limit with 1
-	 * config for 2:2:1. So need to handle both wide plane splitting, and
-	 * two halves of screen splitting for quad-pipe case. Check dest
-	 * rectangle left/right clipping first, then check wide rectangle
-	 * splitting in every half next.
-	 */
-	num_stages = (num_lm + 1) / 2;
-	/* iterate mixer configs for this plane, to separate left/right with the id */
-	for (stage_id = 0; stage_id < num_stages; stage_id++) {
-		struct drm_rect mixer_rect = {
-			.x1 = stage_id * mode->hdisplay / num_stages,
-			.y1 = 0,
-			.x2 = (stage_id + 1) * mode->hdisplay / num_stages,
-			.y2 = mode->vdisplay
-			};
-		int cfg_idx = stage_id * PIPES_PER_STAGE;
-
-		pipe_cfg = &pstate->pipe_cfg[cfg_idx];
-		r_pipe_cfg = &pstate->pipe_cfg[cfg_idx + 1];
-
-		drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
-		pipe_cfg->dst_rect = new_plane_state->dst;
-
-		DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT
-				" vs clip window " DRM_RECT_FMT "\n",
-				DRM_RECT_ARG(&pipe_cfg->src_rect),
-				DRM_RECT_ARG(&mixer_rect));
-
-		/*
-		 * If this plane does not fall into mixer rect, check next
-		 * mixer rect.
-		 */
-		if (!drm_rect_clip_scaled(&pipe_cfg->src_rect,
-					  &pipe_cfg->dst_rect,
-					  &mixer_rect)) {
-			memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg));
-
-			continue;
+	if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
+	     _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
+		if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
+			DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
+					DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
+			return -E2BIG;
 		}
 
-		pipe_cfg->dst_rect.x1 -= mixer_rect.x1;
-		pipe_cfg->dst_rect.x2 -= mixer_rect.x1;
-
-		DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT "\n",
-				DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect));
-
-		/* Split wide rect into 2 rect */
-		if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
-		     _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) {
-
-			if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
-				DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
-						DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
-				return -E2BIG;
-			}
-
-			memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg));
-			pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
-			pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
-			r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
-			r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
-			DPU_DEBUG_PLANE(pdpu, "Split wide plane into:"
-					DRM_RECT_FMT " and " DRM_RECT_FMT "\n",
-					DRM_RECT_ARG(&pipe_cfg->src_rect),
-					DRM_RECT_ARG(&r_pipe_cfg->src_rect));
-		} else {
-			memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg));
-		}
+		*r_pipe_cfg = *pipe_cfg;
+		pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
+		pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
+		r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
+		r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
+	} else {
+		memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg));
+	}
 
-		drm_rect_rotate_inv(&pipe_cfg->src_rect,
-				    new_plane_state->fb->width,
-				    new_plane_state->fb->height,
+	drm_rect_rotate_inv(&pipe_cfg->src_rect,
+			    new_plane_state->fb->width, new_plane_state->fb->height,
+			    new_plane_state->rotation);
+	if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
+		drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
+				    new_plane_state->fb->width, new_plane_state->fb->height,
 				    new_plane_state->rotation);
 
-		if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
-			drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
-					    new_plane_state->fb->width,
-					    new_plane_state->fb->height,
-					    new_plane_state->rotation);
-	}
-
 	pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
 
 	return 0;
@@ -1045,17 +985,20 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
 		drm_atomic_get_new_plane_state(state, plane);
 	struct dpu_plane *pdpu = to_dpu_plane(plane);
 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
-	struct dpu_sw_pipe *pipe;
-	struct dpu_sw_pipe_cfg *pipe_cfg;
-	int ret = 0, i;
+	struct dpu_sw_pipe *pipe = &pstate->pipe[0];
+	struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
+	struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
+	struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
+	int ret = 0;
 
-	for (i = 0; i < PIPES_PER_PLANE; i++) {
-		pipe = &pstate->pipe[i];
-		pipe_cfg = &pstate->pipe_cfg[i];
-		if (!drm_rect_width(&pipe_cfg->src_rect))
-			continue;
-		DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i);
-		ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
+	ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
+					  &crtc_state->adjusted_mode,
+					  new_plane_state);
+	if (ret)
+		return ret;
+
+	if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
+		ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
 						  &crtc_state->adjusted_mode,
 						  new_plane_state);
 		if (ret)

-- 
2.48.1

Re: [PATCH 1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case"

[Marijn Suijten]

On 2025-12-19 12:39:01, Abel Vesa wrote:
> This reverts commit 5978864e34b66bdae4d7613834c03dd5d0a0c891.
> 
> At least on Hamoa based devices, there are IOMMU faults:
> 
> arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x00000000, fsynr=0x3d0023, cbfrsynra=0x1c00, cb=13
> arm-smmu 15000000.iommu: FSR    = 00000402 [Format=2 TF], SID=0x1c00
> arm-smmu 15000000.iommu: FSYNR0 = 003d0023 [S1CBNDX=61 PNU PLVL=3]

I thought that this was normal, and that I was always seeing these on startup
(something to do with framebuffer), but indeed by reverting this patch these
are gone on at least the Xperia XZ2 (regular CMD-mode panel) and XZ3 (CMD-mode
panel, 2:2:1 DSC-merge topology), both sdm845-based phones.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> While on some of these devices, there are also all sorts of artifacts on eDP.
> 
> Reverting this fixes these issues.
> 
> Closes: https://lore.kernel.org/r/z75wnahrp7lrl5yhfdysr3np3qrs6xti2i4otkng4ex3blfgrx@xyiucge3xykb/
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  11 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 137 +++++++++---------------------
>  3 files changed, 40 insertions(+), 110 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index c39f1908ea65..011946bbf5a2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -1620,17 +1620,6 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
>  	return 0;
>  }
>  
> -/**
> - * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline
> - * @state: Pointer to drm crtc state object
> - */
> -unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state)
> -{
> -	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
> -
> -	return cstate->num_mixers;
> -}
> -
>  #ifdef CONFIG_DEBUG_FS
>  static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
>  {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 455073c7025b..2c83f1578fc3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -267,6 +267,4 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type(
>  
>  void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event);
>  
> -unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state);
> -
>  #endif /* _DPU_CRTC_H_ */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index d07a6ab6e7ee..9b7a8b46bfa9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -826,12 +826,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
>  	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
>  	struct dpu_sw_pipe_cfg *pipe_cfg;
>  	struct dpu_sw_pipe_cfg *r_pipe_cfg;
> -	struct dpu_sw_pipe_cfg init_pipe_cfg;
>  	struct drm_rect fb_rect = { 0 };
> -	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>  	uint32_t max_linewidth;
> -	u32 num_lm;
> -	int stage_id, num_stages;
>  
>  	min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO);
>  	max_scale = MAX_DOWNSCALE_RATIO << 16;
> @@ -854,10 +850,13 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
>  		return -EINVAL;
>  	}
>  
> -	num_lm = dpu_crtc_get_num_lm(crtc_state);
> -
> +	/* move the assignment here, to ease handling to another pairs later */
> +	pipe_cfg = &pstate->pipe_cfg[0];
> +	r_pipe_cfg = &pstate->pipe_cfg[1];
>  	/* state->src is 16.16, src_rect is not */
> -	drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src);
> +	drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
> +
> +	pipe_cfg->dst_rect = new_plane_state->dst;
>  
>  	fb_rect.x2 = new_plane_state->fb->width;
>  	fb_rect.y2 = new_plane_state->fb->height;
> @@ -882,94 +881,35 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
>  
>  	max_linewidth = pdpu->catalog->caps->max_linewidth;
>  
> -	drm_rect_rotate(&init_pipe_cfg.src_rect,
> +	drm_rect_rotate(&pipe_cfg->src_rect,
>  			new_plane_state->fb->width, new_plane_state->fb->height,
>  			new_plane_state->rotation);
>  
> -	/*
> -	 * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair
> -	 * configs for left and right half screen in case of 4:4:2 topology.
> -	 * But we may have 2 rect to split wide plane that exceeds limit with 1
> -	 * config for 2:2:1. So need to handle both wide plane splitting, and
> -	 * two halves of screen splitting for quad-pipe case. Check dest
> -	 * rectangle left/right clipping first, then check wide rectangle
> -	 * splitting in every half next.
> -	 */
> -	num_stages = (num_lm + 1) / 2;
> -	/* iterate mixer configs for this plane, to separate left/right with the id */
> -	for (stage_id = 0; stage_id < num_stages; stage_id++) {
> -		struct drm_rect mixer_rect = {
> -			.x1 = stage_id * mode->hdisplay / num_stages,
> -			.y1 = 0,
> -			.x2 = (stage_id + 1) * mode->hdisplay / num_stages,
> -			.y2 = mode->vdisplay
> -			};
> -		int cfg_idx = stage_id * PIPES_PER_STAGE;
> -
> -		pipe_cfg = &pstate->pipe_cfg[cfg_idx];
> -		r_pipe_cfg = &pstate->pipe_cfg[cfg_idx + 1];
> -
> -		drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
> -		pipe_cfg->dst_rect = new_plane_state->dst;
> -
> -		DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT
> -				" vs clip window " DRM_RECT_FMT "\n",
> -				DRM_RECT_ARG(&pipe_cfg->src_rect),
> -				DRM_RECT_ARG(&mixer_rect));
> -
> -		/*
> -		 * If this plane does not fall into mixer rect, check next
> -		 * mixer rect.
> -		 */
> -		if (!drm_rect_clip_scaled(&pipe_cfg->src_rect,
> -					  &pipe_cfg->dst_rect,
> -					  &mixer_rect)) {
> -			memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg));
> -
> -			continue;
> +	if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
> +	     _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
> +		if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
> +			DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
> +					DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
> +			return -E2BIG;
>  		}
>  
> -		pipe_cfg->dst_rect.x1 -= mixer_rect.x1;
> -		pipe_cfg->dst_rect.x2 -= mixer_rect.x1;
> -
> -		DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT "\n",
> -				DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect));
> -
> -		/* Split wide rect into 2 rect */
> -		if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
> -		     _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) {
> -
> -			if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
> -				DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
> -						DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
> -				return -E2BIG;
> -			}
> -
> -			memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg));
> -			pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
> -			pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
> -			r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
> -			r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
> -			DPU_DEBUG_PLANE(pdpu, "Split wide plane into:"
> -					DRM_RECT_FMT " and " DRM_RECT_FMT "\n",
> -					DRM_RECT_ARG(&pipe_cfg->src_rect),
> -					DRM_RECT_ARG(&r_pipe_cfg->src_rect));
> -		} else {
> -			memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg));
> -		}
> +		*r_pipe_cfg = *pipe_cfg;
> +		pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
> +		pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
> +		r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
> +		r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
> +	} else {
> +		memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg));
> +	}
>  
> -		drm_rect_rotate_inv(&pipe_cfg->src_rect,
> -				    new_plane_state->fb->width,
> -				    new_plane_state->fb->height,
> +	drm_rect_rotate_inv(&pipe_cfg->src_rect,
> +			    new_plane_state->fb->width, new_plane_state->fb->height,
> +			    new_plane_state->rotation);
> +	if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
> +		drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
> +				    new_plane_state->fb->width, new_plane_state->fb->height,
>  				    new_plane_state->rotation);
>  
> -		if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
> -			drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
> -					    new_plane_state->fb->width,
> -					    new_plane_state->fb->height,
> -					    new_plane_state->rotation);
> -	}
> -
>  	pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
>  
>  	return 0;
> @@ -1045,17 +985,20 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
>  		drm_atomic_get_new_plane_state(state, plane);
>  	struct dpu_plane *pdpu = to_dpu_plane(plane);
>  	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
> -	struct dpu_sw_pipe *pipe;
> -	struct dpu_sw_pipe_cfg *pipe_cfg;
> -	int ret = 0, i;
> +	struct dpu_sw_pipe *pipe = &pstate->pipe[0];
> +	struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
> +	struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
> +	struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
> +	int ret = 0;
>  
> -	for (i = 0; i < PIPES_PER_PLANE; i++) {
> -		pipe = &pstate->pipe[i];
> -		pipe_cfg = &pstate->pipe_cfg[i];
> -		if (!drm_rect_width(&pipe_cfg->src_rect))
> -			continue;
> -		DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i);
> -		ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
> +	ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
> +					  &crtc_state->adjusted_mode,
> +					  new_plane_state);
> +	if (ret)
> +		return ret;
> +
> +	if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
> +		ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
>  						  &crtc_state->adjusted_mode,
>  						  new_plane_state);
>  		if (ret)
> 
> -- 
> 2.48.1
> 

Re: [PATCH 1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case"

[Konrad Dybcio]

On 12/19/25 8:55 PM, Marijn Suijten wrote:
> On 2025-12-19 12:39:01, Abel Vesa wrote:
>> This reverts commit 5978864e34b66bdae4d7613834c03dd5d0a0c891.
>>
>> At least on Hamoa based devices, there are IOMMU faults:
>>
>> arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x00000000, fsynr=0x3d0023, cbfrsynra=0x1c00, cb=13
>> arm-smmu 15000000.iommu: FSR    = 00000402 [Format=2 TF], SID=0x1c00
>> arm-smmu 15000000.iommu: FSYNR0 = 003d0023 [S1CBNDX=61 PNU PLVL=3]
> 
> I thought that this was normal, and that I was always seeing these on startup
> (something to do with framebuffer), but indeed by reverting this patch these
> are gone on at least the Xperia XZ2 (regular CMD-mode panel) and XZ3 (CMD-mode
> panel, 2:2:1 DSC-merge topology), both sdm845-based phones.

This is very close to what you've seen, but note this one comes with
iova = 0, meaning we're likely passing some garbage somewhere

Konrad

Re: [PATCH 1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case"

[Dmitry Baryshkov]

On Fri, Dec 19, 2025 at 12:39:01PM +0200, Abel Vesa wrote:
> This reverts commit 5978864e34b66bdae4d7613834c03dd5d0a0c891.
> 
> At least on Hamoa based devices, there are IOMMU faults:
> 
> arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x00000000, fsynr=0x3d0023, cbfrsynra=0x1c00, cb=13
> arm-smmu 15000000.iommu: FSR    = 00000402 [Format=2 TF], SID=0x1c00
> arm-smmu 15000000.iommu: FSYNR0 = 003d0023 [S1CBNDX=61 PNU PLVL=3]
> 
> While on some of these devices, there are also all sorts of artifacts on eDP.
> 
> Reverting this fixes these issues.
> 
> Closes: https://lore.kernel.org/r/z75wnahrp7lrl5yhfdysr3np3qrs6xti2i4otkng4ex3blfgrx@xyiucge3xykb/
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Fixes: 5978864e34b6 ("drm/msm/dpu: support plane splitting in quad-pipe case")

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  11 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 137 +++++++++---------------------
>  3 files changed, 40 insertions(+), 110 deletions(-)
> 

-- 
With best wishes
Dmitry

Re: [PATCH 1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case"

[Jun Nie]

Abel Vesa <abel.vesa@oss.qualcomm.com> 于2025年12月19日周五 18:39写道：
>
> This reverts commit 5978864e34b66bdae4d7613834c03dd5d0a0c891.
>
> At least on Hamoa based devices, there are IOMMU faults:
>
> arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x00000000, fsynr=0x3d0023, cbfrsynra=0x1c00, cb=13
> arm-smmu 15000000.iommu: FSR    = 00000402 [Format=2 TF], SID=0x1c00
> arm-smmu 15000000.iommu: FSYNR0 = 003d0023 [S1CBNDX=61 PNU PLVL=3]
>
> While on some of these devices, there are also all sorts of artifacts on eDP.

Hi Abel,

Could you help check what's the pipe topology of your eDP case? I need
to reproduce the issue.
Or could you help share the content of
/sys/kernel/debug/dri/ae01000.display-controller/state?
Thanks!

Regards,
Jun

[PATCH 2/2] Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case"

[Abel Vesa]

This reverts commit d7ec9366b15cd04508fa015cb94d546b1c01edfb.

The dual-DSI dual-DSC scenario seems to be broken by this commit.

Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
Closes: https://lore.kernel.org/r/aUR2b3FOSisTfDFj@SoMainline.org
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         | 27 ++++++----------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |  6 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      | 29 ++++++++++++++++--------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |  2 +-
 6 files changed, 33 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 011946bbf5a2..2d06c950e814 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
 		struct dpu_crtc_state *crtc_state)
 {
 	struct dpu_crtc_mixer *m;
-	u32 crcs[CRTC_QUAD_MIXERS];
+	u32 crcs[CRTC_DUAL_MIXERS];
 
 	int rc = 0;
 	int i;
@@ -1328,7 +1328,6 @@ static struct msm_display_topology dpu_crtc_get_topology(
 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 	struct msm_display_topology topology = {0};
 	struct drm_encoder *drm_enc;
-	u32 num_rt_intf;
 
 	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
 		dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
@@ -1342,14 +1341,11 @@ static struct msm_display_topology dpu_crtc_get_topology(
 	 * Dual display
 	 * 2 LM, 2 INTF ( Split display using 2 interfaces)
 	 *
-	 * If DSC is enabled, try to use 4:4:2 topology if there is enough
-	 * resource. Otherwise, use 2:2:2 topology.
-	 *
 	 * Single display
 	 * 1 LM, 1 INTF
 	 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
 	 *
-	 * If DSC is enabled, use 2:2:1 topology
+	 * If DSC is enabled, use 2 LMs for 2:2:1 topology
 	 *
 	 * Add dspps to the reservation requirements if ctm is requested
 	 *
@@ -1361,23 +1357,14 @@ static struct msm_display_topology dpu_crtc_get_topology(
 	 * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
 	 */
 
-	num_rt_intf = topology.num_intf;
-	if (topology.cwb_enabled)
-		num_rt_intf--;
-
-	if (topology.num_dsc) {
-		if (dpu_kms->catalog->dsc_count >= num_rt_intf * 2)
-			topology.num_dsc = num_rt_intf * 2;
-		else
-			topology.num_dsc = num_rt_intf;
-		topology.num_lm = topology.num_dsc;
-	} else if (num_rt_intf == 2) {
+	if (topology.num_intf == 2 && !topology.cwb_enabled)
+		topology.num_lm = 2;
+	else if (topology.num_dsc == 2)
 		topology.num_lm = 2;
-	} else if (dpu_kms->catalog->caps->has_3d_merge) {
+	else if (dpu_kms->catalog->caps->has_3d_merge)
 		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
-	} else {
+	else
 		topology.num_lm = 1;
-	}
 
 	if (crtc_state->ctm)
 		topology.num_dspp = topology.num_lm;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 2c83f1578fc3..94392b9b9245 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -210,7 +210,7 @@ struct dpu_crtc_state {
 
 	bool bw_control;
 	bool bw_split_vote;
-	struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];
+	struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
 
 	uint64_t input_fence_timeout_ns;
 
@@ -218,10 +218,10 @@ struct dpu_crtc_state {
 
 	/* HW Resources reserved for the crtc */
 	u32 num_mixers;
-	struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];
+	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
 
 	u32 num_ctls;
-	struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];
+	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
 
 	enum dpu_crtc_crc_source crc_source;
 	int crc_frame_skip_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d1cfe81a3373..9f3957f24c6a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -55,7 +55,7 @@
 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
 	(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
 
-#define MAX_CHANNELS_PER_ENC 4
+#define MAX_CHANNELS_PER_ENC 2
 #define MAX_CWB_PER_ENC 2
 
 #define IDLE_SHORT_TIMEOUT	1
@@ -661,6 +661,7 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
 	struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
 	struct msm_display_info *disp_info = &dpu_enc->disp_info;
+	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
 	struct drm_connector *connector;
 	struct drm_connector_state *conn_state;
 	struct drm_framebuffer *fb;
@@ -674,12 +675,22 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
 
 	dsc = dpu_encoder_get_dsc_config(drm_enc);
 
-	/*
-	 * Set DSC number as 1 to mark the enabled status, will be adjusted
-	 * in dpu_crtc_get_topology()
-	 */
-	if (dsc)
-		topology->num_dsc = 1;
+	/* We only support 2 DSC mode (with 2 LM and 1 INTF) */
+	if (dsc) {
+		/*
+		 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
+		 * when Display Stream Compression (DSC) is enabled,
+		 * and when enough DSC blocks are available.
+		 * This is power-optimal and can drive up to (including) 4k
+		 * screens.
+		 */
+		WARN(topology->num_intf > 2,
+		     "DSC topology cannot support more than 2 interfaces\n");
+		if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
+			topology->num_dsc = 2;
+		else
+			topology->num_dsc = 1;
+	}
 
 	connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
 	if (!connector)
@@ -2169,8 +2180,8 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
 {
 	int i, num_lm;
 	struct dpu_global_state *global_state;
-	struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
-	struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];
+	struct dpu_hw_blk *hw_lm[2];
+	struct dpu_hw_mixer *hw_mixer[2];
 	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
 
 	/* reset all mixers for this encoder */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 09395d7910ac..61b22d949454 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
 
 	/* Use merge_3d unless DSC MERGE topology is used */
 	if (phys_enc->split_role == ENC_ROLE_SOLO &&
-	    (dpu_cstate->num_mixers != 1) &&
+	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
 	    !dpu_encoder_use_dsc_merge(phys_enc->parent))
 		return BLEND_3D_H_ROW_INT;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 336757103b5a..4964e70610d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -24,7 +24,7 @@
 #define DPU_MAX_IMG_WIDTH 0x3fff
 #define DPU_MAX_IMG_HEIGHT 0x3fff
 
-#define CRTC_QUAD_MIXERS	4
+#define CRTC_DUAL_MIXERS	2
 
 #define MAX_XIN_COUNT 16
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 31451241f083..046b683d4c66 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -34,7 +34,7 @@
 #define DPU_MAX_PLANES			4
 #endif
 
-#define STAGES_PER_PLANE		2
+#define STAGES_PER_PLANE		1
 #define PIPES_PER_STAGE			2
 #define PIPES_PER_PLANE			(PIPES_PER_STAGE * STAGES_PER_PLANE)
 #ifndef DPU_MAX_DE_CURVES

-- 
2.48.1

Re: [PATCH 2/2] Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case"

[Marijn Suijten]

On 19 December 2025 11:39:02 CET, Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
>This reverts commit d7ec9366b15cd04508fa015cb94d546b1c01edfb.
>
>The dual-DSI dual-DSC scenario seems to be broken by this commit.
>
>Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
>Closes: https://lore.kernel.org/r/aUR2b3FOSisTfDFj@SoMainline.org
>Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Thanks! That kicks off one dependency for actually sending this 2:2:2 panel and DTS for the Sony Xperia 1 III and onwards.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

>---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         | 27 ++++++----------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |  6 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      | 29 ++++++++++++++++--------
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |  2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |  2 +-
> 6 files changed, 33 insertions(+), 35 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>index 011946bbf5a2..2d06c950e814 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>@@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
> 		struct dpu_crtc_state *crtc_state)
> {
> 	struct dpu_crtc_mixer *m;
>-	u32 crcs[CRTC_QUAD_MIXERS];
>+	u32 crcs[CRTC_DUAL_MIXERS];
> 
> 	int rc = 0;
> 	int i;
>@@ -1328,7 +1328,6 @@ static struct msm_display_topology dpu_crtc_get_topology(
> 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> 	struct msm_display_topology topology = {0};
> 	struct drm_encoder *drm_enc;
>-	u32 num_rt_intf;
> 
> 	drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
> 		dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
>@@ -1342,14 +1341,11 @@ static struct msm_display_topology dpu_crtc_get_topology(
> 	 * Dual display
> 	 * 2 LM, 2 INTF ( Split display using 2 interfaces)
> 	 *
>-	 * If DSC is enabled, try to use 4:4:2 topology if there is enough
>-	 * resource. Otherwise, use 2:2:2 topology.
>-	 *
> 	 * Single display
> 	 * 1 LM, 1 INTF
> 	 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
> 	 *
>-	 * If DSC is enabled, use 2:2:1 topology
>+	 * If DSC is enabled, use 2 LMs for 2:2:1 topology
> 	 *
> 	 * Add dspps to the reservation requirements if ctm is requested
> 	 *
>@@ -1361,23 +1357,14 @@ static struct msm_display_topology dpu_crtc_get_topology(
> 	 * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
> 	 */
> 
>-	num_rt_intf = topology.num_intf;
>-	if (topology.cwb_enabled)
>-		num_rt_intf--;
>-
>-	if (topology.num_dsc) {
>-		if (dpu_kms->catalog->dsc_count >= num_rt_intf * 2)
>-			topology.num_dsc = num_rt_intf * 2;
>-		else
>-			topology.num_dsc = num_rt_intf;
>-		topology.num_lm = topology.num_dsc;
>-	} else if (num_rt_intf == 2) {
>+	if (topology.num_intf == 2 && !topology.cwb_enabled)
>+		topology.num_lm = 2;
>+	else if (topology.num_dsc == 2)
> 		topology.num_lm = 2;
>-	} else if (dpu_kms->catalog->caps->has_3d_merge) {
>+	else if (dpu_kms->catalog->caps->has_3d_merge)
> 		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
>-	} else {
>+	else
> 		topology.num_lm = 1;
>-	}
> 
> 	if (crtc_state->ctm)
> 		topology.num_dspp = topology.num_lm;
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>index 2c83f1578fc3..94392b9b9245 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>@@ -210,7 +210,7 @@ struct dpu_crtc_state {
> 
> 	bool bw_control;
> 	bool bw_split_vote;
>-	struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];
>+	struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
> 
> 	uint64_t input_fence_timeout_ns;
> 
>@@ -218,10 +218,10 @@ struct dpu_crtc_state {
> 
> 	/* HW Resources reserved for the crtc */
> 	u32 num_mixers;
>-	struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];
>+	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> 
> 	u32 num_ctls;
>-	struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];
>+	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
> 
> 	enum dpu_crtc_crc_source crc_source;
> 	int crc_frame_skip_count;
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>index d1cfe81a3373..9f3957f24c6a 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>@@ -55,7 +55,7 @@
> #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
> 	(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
> 
>-#define MAX_CHANNELS_PER_ENC 4
>+#define MAX_CHANNELS_PER_ENC 2
> #define MAX_CWB_PER_ENC 2
> 
> #define IDLE_SHORT_TIMEOUT	1
>@@ -661,6 +661,7 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
> 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
> 	struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
> 	struct msm_display_info *disp_info = &dpu_enc->disp_info;
>+	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
> 	struct drm_connector *connector;
> 	struct drm_connector_state *conn_state;
> 	struct drm_framebuffer *fb;
>@@ -674,12 +675,22 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
> 
> 	dsc = dpu_encoder_get_dsc_config(drm_enc);
> 
>-	/*
>-	 * Set DSC number as 1 to mark the enabled status, will be adjusted
>-	 * in dpu_crtc_get_topology()
>-	 */
>-	if (dsc)
>-		topology->num_dsc = 1;
>+	/* We only support 2 DSC mode (with 2 LM and 1 INTF) */
>+	if (dsc) {
>+		/*
>+		 * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
>+		 * when Display Stream Compression (DSC) is enabled,
>+		 * and when enough DSC blocks are available.
>+		 * This is power-optimal and can drive up to (including) 4k
>+		 * screens.
>+		 */
>+		WARN(topology->num_intf > 2,
>+		     "DSC topology cannot support more than 2 interfaces\n");
>+		if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
>+			topology->num_dsc = 2;
>+		else
>+			topology->num_dsc = 1;
>+	}
> 
> 	connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
> 	if (!connector)
>@@ -2169,8 +2180,8 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
> {
> 	int i, num_lm;
> 	struct dpu_global_state *global_state;
>-	struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
>-	struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];
>+	struct dpu_hw_blk *hw_lm[2];
>+	struct dpu_hw_mixer *hw_mixer[2];
> 	struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
> 
> 	/* reset all mixers for this encoder */
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>index 09395d7910ac..61b22d949454 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>@@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> 
> 	/* Use merge_3d unless DSC MERGE topology is used */
> 	if (phys_enc->split_role == ENC_ROLE_SOLO &&
>-	    (dpu_cstate->num_mixers != 1) &&
>+	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
> 	    !dpu_encoder_use_dsc_merge(phys_enc->parent))
> 		return BLEND_3D_H_ROW_INT;
> 
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>index 336757103b5a..4964e70610d1 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>@@ -24,7 +24,7 @@
> #define DPU_MAX_IMG_WIDTH 0x3fff
> #define DPU_MAX_IMG_HEIGHT 0x3fff
> 
>-#define CRTC_QUAD_MIXERS	4
>+#define CRTC_DUAL_MIXERS	2
> 
> #define MAX_XIN_COUNT 16
> 
>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>index 31451241f083..046b683d4c66 100644
>--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>@@ -34,7 +34,7 @@
> #define DPU_MAX_PLANES			4
> #endif
> 
>-#define STAGES_PER_PLANE		2
>+#define STAGES_PER_PLANE		1
> #define PIPES_PER_STAGE			2
> #define PIPES_PER_PLANE			(PIPES_PER_STAGE * STAGES_PER_PLANE)
> #ifndef DPU_MAX_DE_CURVES
>

Re: [PATCH 2/2] Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case"

[Dmitry Baryshkov]

On Fri, Dec 19, 2025 at 12:39:02PM +0200, Abel Vesa wrote:
> This reverts commit d7ec9366b15cd04508fa015cb94d546b1c01edfb.
> 
> The dual-DSI dual-DSC scenario seems to be broken by this commit.
> 
> Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
> Closes: https://lore.kernel.org/r/aUR2b3FOSisTfDFj@SoMainline.org
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         | 27 ++++++----------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |  6 ++---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      | 29 ++++++++++++++++--------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |  2 +-
>  6 files changed, 33 insertions(+), 35 deletions(-)

Fixes: d7ec9366b15c ("drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case")

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>



-- 
With best wishes
Dmitry

Re: [PATCH 0/2] drm/msm/dpu: Revert broken parts of the quad pipe support

[Dmitry Baryshkov]

On Fri, 19 Dec 2025 12:39:00 +0200, Abel Vesa wrote:
> There are quite a few reports off-list that, at least on Hamoa based
> devices, there are some IOMMU faults and some abnormal artifacts on eDP.
> These have been traced to the quad pipe support introduced in 6.19-rc1.
> 
> Meanwhile, Marijn reported some issues in some dual-DSI dual-DSC scenario.
> 
> Off-list discussion concluded into reverting these two commits to avoid
> the described issues.
> 
> [...]

Applied to msm-fixes, thanks!

[1/2] Revert "drm/msm/dpu: support plane splitting in quad-pipe case"
      https://gitlab.freedesktop.org/lumag/msm/-/commit/35ab5123bd24
[2/2] Revert "drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case"
      https://gitlab.freedesktop.org/lumag/msm/-/commit/da9168d8ef1c

Best regards,
-- 
With best wishes
Dmitry