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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-88d9a44e26bsm86467836d6.47.2025.12.22.10.48.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 10:48:49 -0800 (PST) Date: Mon, 22 Dec 2025 13:48:43 -0500 From: Brian Masney To: Junhui Liu Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Troy Mitchell Subject: Re: [PATCH v3 1/6] clk: correct clk_div_mask() return value for width == 32 Message-ID: References: <20251216-dr1v90-cru-v3-0-52cc938d1db0@pigmoral.tech> <20251216-dr1v90-cru-v3-1-52cc938d1db0@pigmoral.tech> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251216-dr1v90-cru-v3-1-52cc938d1db0@pigmoral.tech> User-Agent: Mutt/2.2.14 (2025-02-20) On Tue, Dec 16, 2025 at 11:39:41AM +0800, Junhui Liu wrote: > The macro clk_div_mask() currently wraps to zero when width is 32 due to > 1 << 32 being undefined behavior. This leads to incorrect mask generation > and prevents correct retrieval of register field values for 32-bit-wide > dividers. > > Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely > on a 32-bit val entry in their div_table to match a div, so providing a > full 32-bit mask is necessary. > > Fix this by casting 1 to long, ensuring proper behavior for valid widths up > to 32. > > Reviewed-by: Troy Mitchell > Signed-off-by: Junhui Liu Reviewed-by: Brian Masney