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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-88d96bec097sm117191926d6.16.2025.12.23.18.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Dec 2025 18:25:20 -0800 (PST) Date: Wed, 24 Dec 2025 10:25:10 +0800 From: yuanjiey To: Dmitry Baryshkov Cc: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: Re: [PATCH v4 10/11] drm/msm/dpu: Add Kaanapali SSPP sub-block support Message-ID: References: <20251222102400.1109-1-yuanjie.yang@oss.qualcomm.com> <20251222102400.1109-11-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: LjFAJ5GYqGz132LRnGwteyAAqgfapOp6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI0MDAxOCBTYWx0ZWRfX6ZVTH0bpV4X/ SKXAqsPTj51hA3EKf4a5MvCQiVD7pyXhP5P3lzv0BkFRsxP3T/pGb1w5fZ1rSnMal1USITi697a +RccM9c6iQfJKSrqRq9Xb0Rm65ft2UO9CFeujYBJjRr6Ip0lrNk2zJX0PIhZSfgdJ8GKtwcHW+n OegAyov4W2DtR8inz/ELX/LmpzEVLGAbnQ1CnVu3ASvF98LRPHmugsUTJ5s8BZRs/sArcVfGF0r FEYjO0dCag1Mm7JJavM+pDWXsVUC/oUl6HLXl/i4v58KZw2cIBPwuOUYODGx42JX9h8HbCGSLLQ a4G1k1MUdLmyGbHYz6zWhd8hXnPgCakT9M5JE/YY4xMFliPDLyZkkeAVA42J/zdTUM5QTdpjXxt vzAN4PHpbsl0eUY66ltZhuK0ElT0oNwKu/g0iIMljCQkSvaElzN1yphDiihXcR1kc5tZDka5+dH OlEhnD++T9lRO2sIqGg== X-Proofpoint-GUID: LjFAJ5GYqGz132LRnGwteyAAqgfapOp6 X-Authority-Analysis: v=2.4 cv=NZDrFmD4 c=1 sm=1 tr=0 ts=694b4f12 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=kj9zAlcOel0A:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=EeaRNE0bk9nq3hHqtxUA:9 a=CjuIK1q_8ugA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-24_01,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512240018 On Tue, Dec 23, 2025 at 10:30:56PM +0200, Dmitry Baryshkov wrote: > On Mon, Dec 22, 2025 at 06:23:59PM +0800, yuanjie yang wrote: > > From: Yuanjie Yang > > > > Add support for Kaanapali platform SSPP sub-blocks, which > > introduce structural changes including register additions, > > removals, and relocations. Add the new common and rectangle > > blocks, and update register definitions and handling to > > ensure compatibility with DPU v13.0. > > > > Co-developed-by: Yongxing Mou > > Signed-off-by: Yongxing Mou > > Signed-off-by: Yuanjie Yang > > --- > > drivers/gpu/drm/msm/Makefile | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 13 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 + > > .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 17 +- > > 7 files changed, 371 insertions(+), 6 deletions(-) > > create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c > > > > > @@ -291,9 +292,10 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format > > if (MSM_FORMAT_IS_UBWC(fmt)) > > opmode |= MDSS_MDP_OP_BWC_EN; > > src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ > > - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, > > - DPU_FETCH_CONFIG_RESET_VALUE | > > - ctx->ubwc->highest_bank_bit << 18); > > + if (core_major_ver < 13) > > + DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, > > + DPU_FETCH_CONFIG_RESET_VALUE | > > + ctx->ubwc->highest_bank_bit << 18); > > I'd prefer if this is pulled into dpu_hw_sspp_setup_format(). OK, will put this part in dpu_hw_sspp_setup_format. > > switch (ctx->ubwc->ubwc_enc_version) { > > case UBWC_1_0: > > fast_clear = fmt->alpha_enable ? BIT(31) : 0; > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c > > index 478a091aeccf..006dcc4a0dcc 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c > > This commit was about SSPPs. Why are you touching WB? Look like I should drop WB part in current patch, and add a new patch just "add qos V13 in WB". make it more clear for each patch function. Thank, Yuanjie > > @@ -148,6 +148,15 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, > > cfg); > > } > > > > +static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx, > > + struct dpu_hw_qos_cfg *cfg) > > +{ > > + if (!ctx || !cfg) > > + return; > > + > > + _dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg); > > +} > > + > > static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, > > const struct msm_format *fmt, > > bool enable) > > @@ -202,8 +211,12 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, > > if (test_bit(DPU_WB_XY_ROI_OFFSET, &features)) > > ops->setup_roi = dpu_hw_wb_roi; > > > > - if (test_bit(DPU_WB_QOS, &features)) > > - ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut; > > + if (test_bit(DPU_WB_QOS, &features)) { > > + if (mdss_rev->core_major_ver >= 13) > > + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13; > > + else > > + ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut; > > + } > > > > if (test_bit(DPU_WB_CDP, &features)) > > ops->setup_cdp = dpu_hw_wb_setup_cdp; > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry