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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3812251b2b0sm75897681fa.18.2025.12.28.02.34.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Dec 2025 02:34:50 -0800 (PST) Date: Sun, 28 Dec 2025 11:34:49 +0100 From: Marcus Folkesson To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: Re: [PATCH RESEND v3 0/5] I2C Mux per channel bus speed Message-ID: References: <20251202-i2c-mux-v3-0-877dcf478a9f@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="7rFkj6zIm9eFzZmB" Content-Disposition: inline In-Reply-To: <20251202-i2c-mux-v3-0-877dcf478a9f@gmail.com> --7rFkj6zIm9eFzZmB Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Dec 02, 2025 at 09:09:47AM +0100, Marcus Folkesson wrote: > This was a RFC on how to implement a feature to have different bus > speeds on different channels with an I2C multiplexer/switch. > As no major complaints on the design came up during the review, I > decided to submit the series without the RFC tag. >=20 > The benefit with this feature is that you may group devices after > the fastest bus speed they can handle. > A real-world example is that you could have e.g. a display running @400kHz > and a smart battery running @100kHz using the same I2C controller. >=20 > There are many corner cases where this may cause a problem for some > hardware topologies. I've tried to describe those I could think of > in the documentation, see Patch #5. >=20 > E.g. one risk is that if the mux driver does not disconnect channels > when Idle, this may cause a higher frequency to "leak" through to > devices that are supposed to run at lower bus speed. > This is not only a "problem" for changing bus speed but could also be > an issue for potential address conflicts. >=20 > The implementation is split up into several patches: >=20 > Patch #1 Introduce a callback for the i2c controller to set bus speed > Patch #2 Introduce functionality to adjust bus speed depending on mux > channel. > Patch #3 Cleanup i2c-davinci driver a bit to prepare it for set_clk_freq > Parch #4 Implement set_clk_freq for the i2c-davinci driver > Parch #5 Update documentation with this feature >=20 > Signed-off-by: Marcus Folkesson Ping on this series. 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