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Thu, 01 Jan 2026 00:27:18 -0800 (PST) Date: Thu, 1 Jan 2026 16:27:13 +0800 From: Kuan-Wei Chiu To: Lucas Wei Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , sjadavani@google.com, kernel test robot , stable@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, visitorckw@google.com, marscheng@google.com Subject: Re: [PATCH v2] arm64: errata: Workaround for SI L1 downstream coherency issue Message-ID: References: <20251229033621.996546-1-lucaswei@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251229033621.996546-1-lucaswei@google.com> Hi Lucas, On Mon, Dec 29, 2025 at 03:36:19AM +0000, Lucas Wei wrote: > When software issues a Cache Maintenance Operation (CMO) targeting a > dirty cache line, the CPU and DSU cluster may optimize the operation by > combining the CopyBack Write and CMO into a single combined CopyBack > Write plus CMO transaction presented to the interconnect (MCN). > For these combined transactions, the MCN splits the operation into two > separate transactions, one Write and one CMO, and then propagates the > write and optionally the CMO to the downstream memory system or external > Point of Serialization (PoS). > However, the MCN may return an early CompCMO response to the DSU cluster > before the corresponding Write and CMO transactions have completed at > the external PoS or downstream memory. As a result, stale data may be > observed by external observers that are directly connected to the > external PoS or downstream memory. > > This erratum affects any system topology in which the following > conditions apply: > - The Point of Serialization (PoS) is located downstream of the > interconnect. > - A downstream observer accesses memory directly, bypassing the > interconnect. > > Conditions: > This erratum occurs only when all of the following conditions are met: > 1. Software executes a data cache maintenance operation, specifically, > a clean or invalidate by virtual address (DC CVAC, DC CIVAC, or DC > IVAC), that hits on unique dirty data in the CPU or DSU cache. This > results in a combined CopyBack and CMO being issued to the > interconnect. > 2. The interconnect splits the combined transaction into separate Write > and CMO transactions and returns an early completion response to the > CPU or DSU before the write has completed at the downstream memory > or PoS. > 3. A downstream observer accesses the affected memory address after the > early completion response is issued but before the actual memory > write has completed. This allows the observer to read stale data > that has not yet been updated at the PoS or downstream memory. > > The implementation of workaround put a second loop of CMOs at the same > virtual address whose operation meet erratum conditions to wait until > cache data be cleaned to PoC.. This way of implementation mitigates > performance panalty compared to purly duplicate orignial CMO. > > Reported-by: kernel test robot I assume the Reported-by tag was added due to the sparse warning in v1? Since this patch fixes a hardware erratum rather than an issue reported by the robot, I don't think we need this tag here. Generally, we don't add Reported-by for fixing robot warnings across patch versions. Regards, Kuan-Wei