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[104.155.85.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4324e9ba877sm86824635f8f.0.2026.01.02.10.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jan 2026 10:27:09 -0800 (PST) Date: Fri, 2 Jan 2026 18:27:06 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, joro@8bytes.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, skolothumtho@nvidia.com, praan@google.com, xueshuai@linux.alibaba.com Subject: Re: [PATCH rc v5 2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence Message-ID: References: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1766093909.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1766093909.git.nicolinc@nvidia.com> On Thu, Dec 18, 2025 at 01:41:57PM -0800, Nicolin Chen wrote: > From: Jason Gunthorpe > > Nested CD tables set the MEV bit to try to reduce multi-fault spamming on > the hypervisor. Since MEV is in STE word 1 this causes a breaking update > sequence that is not required and impacts real workloads. > > For the purposes of STE updates the value of MEV doesn't matter, if it is > set/cleared early or late it just results in a change to the fault reports > that must be supported by the kernel anyhow. The spec says: > > Note: Software must expect, and be able to deal with, coalesced fault > records even when MEV == 0. > > So mark STE MEV safe when computing the update sequence, to avoid creating > a breaking update. > > Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations") > Cc: stable@vger.kernel.org > Signed-off-by: Jason Gunthorpe > Reviewed-by: Shuai Xue > Signed-off-by: Nicolin Chen Reviewed-by: Mostafa Saleh Thanks, Mostafa > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 8dbf4ad5b51e..12a9669bcc83 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); > VISIBLE_IF_KUNIT > void arm_smmu_get_ste_update_safe(__le64 *safe_bits) > { > + /* > + * MEV does not meaningfully impact the operation of the HW, it only > + * changes how many fault events are generated, thus we can relax it > + * when computing the ordering. The spec notes the device can act like > + * MEV=1 anyhow: > + * > + * Note: Software must expect, and be able to deal with, coalesced > + * fault records even when MEV == 0. > + */ > + safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV); > } > EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe); > > -- > 2.43.0 >