Re: [PATCH v1 09/13] arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid()

Linu Cherian
2026-01-06T03:25:49Z

On Tue, Dec 16, 2025 at 02:45:54PM +0000, Ryan Roberts wrote
> Now that we have __tlbi_level_asid(), let's refactor the
> *flush_tlb_page*() variants to use it rather than open coding.
>
> The emitted tlbi(s) is/are intended to be exactly the same as before; no
> TTL hint is provided. Although the spec for flush_tlb_page() allows for
> setting the TTL hint to 3, it turns out that
> flush_tlb_fix_spurious_fault_pmd() depends on
> local_flush_tlb_page_nonotify() to invalidate the level 2 entry. This
> will be fixed separately.
>
> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
> ---
> arch/arm64/include/asm/tlbflush.h | 12 ++----------
> 1 file changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 3b72a71feac0..37c782ddc149 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -327,12 +327,8 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
> static inline void __local_flush_tlb_page_nonotify_nosync(struct mm_struct *mm,
> unsigned long uaddr)
> {
> - unsigned long addr;
> -
> dsb(nshst);
> - addr = __TLBI_VADDR(uaddr, ASID(mm));
> - __tlbi(vale1, addr);
> - __tlbi_user(vale1, addr);
> + __tlbi_level_asid(vale1, uaddr, TLBI_TTL_UNKNOWN, ASID(mm));
> }
>
> static inline void local_flush_tlb_page_nonotify(struct vm_area_struct *vma,
> @@ -354,12 +350,8 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma,
> static inline void __flush_tlb_page_nosync(struct mm_struct *mm,
> unsigned long uaddr)
> {
> - unsigned long addr;
> -
> dsb(ishst);
> - addr = __TLBI_VADDR(uaddr, ASID(mm));
> - __tlbi(vale1is, addr);
> - __tlbi_user(vale1is, addr);
> + __tlbi_level_asid(vale1is, uaddr, TLBI_TTL_UNKNOWN, ASID(mm));
> mmu_notifier_arch_invalidate_secondary_tlbs(mm, uaddr & PAGE_MASK,
> (uaddr & PAGE_MASK) + PAGE_SIZE);
> }

Reviewed-by: Linu Cherian <linu.cherian@arm.com>