From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 116AF449EDC for ; Tue, 20 Jan 2026 14:07:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768918061; cv=none; b=UoYIY/1AB8S/ow9QNxsO0MUTw3ciAXJBiZPr73GoOV+NRSiV/og6tH33TacN73HYVb2uSQHWapmgYxdwn/y285QDFTSptD5C+ug7CEQccSjiPk+HbMMVZxgFl2QafGX1pRxxJ6aII3ewdiNEt3aJMs88felrT9orN9CMHPCkkvM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768918061; c=relaxed/simple; bh=bTP/+NU/ZnbmIO7n1SfYghrRQq/5oN4tWNW770Y+f2M=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=dx2Km6DfNemez34yOI/nntgpibOZrSorVzP7dfmzTvQRphI5klWuiKaKAAfHCDodEjKA9LJElTvFL9gn4KAH5sNV5Yelbq9teuzUs3nRqB12JobiT14lZnHASIaa4gyjoh8RNUDwkKdT6WAlvZO+/8bECQftAnLaMwI1h+7p4a4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KkqHGmjs; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KkqHGmjs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768918057; x=1800454057; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=bTP/+NU/ZnbmIO7n1SfYghrRQq/5oN4tWNW770Y+f2M=; b=KkqHGmjs+BbzST4IH0OciJUyGYr0H2Z0lyI9xRCpxS/R9I1+WMwFR1bK KICYfMUuZniU/qIg5qIQKBIlhf5WUSTF4rT541nfA01tm1cksrEJqJf7H jQQvkLvq7C0sFm9GKR9e2Y7faVvK8KB7uVOMdS7Q65/tEdH1gfpMQc+4B 5AxeNvZaII2OKTyn9iHuc38ayOW5CB5h5UTh/+TOjx9vsLq87Y/6R1Cth TZoNdNL935DEeUqFYaUVO+y2jv3f8lGJYCOTb/FrS7UnOT1adQRBGhdm7 AqOnX1XOyTK9Fmnk94cvQHKm8+vAVvlzcTn0vSpiAIp4I+vKuWLn+N/Aw g==; X-CSE-ConnectionGUID: uK2rsHgYSie+uQyXMEFZng== X-CSE-MsgGUID: jSz1Hp14T/SG/c9xyHPNrg== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="70031433" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="70031433" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 06:07:37 -0800 X-CSE-ConnectionGUID: CVA00xa3S4W9iMWh5cJThg== X-CSE-MsgGUID: cVuO5X2hQlWzkI4REBjLyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="210279201" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.39]) by orviesa003.jf.intel.com with ESMTP; 20 Jan 2026 06:07:33 -0800 Date: Tue, 20 Jan 2026 22:33:04 +0800 From: Zhao Liu To: Dave Hansen Cc: linux-kernel@vger.kernel.org, sohil.mehta@intel.com, Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org Subject: Re: [PATCH 6/6] x86/microcode: Add platform mask to Intel microcode "old" list Message-ID: References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> <20260119195100.C96636C3@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260119195100.C96636C3@davehans-spike.ostc.intel.com> On Mon, Jan 19, 2026 at 11:51:00AM -0800, Dave Hansen wrote: > Date: Mon, 19 Jan 2026 11:51:00 -0800 > From: Dave Hansen > Subject: [PATCH 6/6] x86/microcode: Add platform mask to Intel microcode > "old" list > > > From: Dave Hansen > > Intel sometimes has CPUs with identical family/model/stepping but > which need different microcode. These CPUs are differentiated with the > platform ID. > > The Intel "microcode-20250512" release was used to generate the > existing contents of intel-ucode-defs.h. Use that same release and add > the platform mask to the definitions. > > This makes the list a few entries longer. For example for the ancient > Pentium III there are two CPUs that differ only in their platform and > have two different microcode versions: > > { ..., .model = 0x05, .steppings = 0x0001, .platform_mask = 0x01, .driver_data = 0x40 }, > { ..., .model = 0x05, .steppings = 0x0001, .platform_mask = 0x08, .driver_data = 0x45 }, > > These CPUs previously shared a definition. Another example is the > state-of-the-art Granite Rapids: > > { ..., .model = 0xad, .steppings = 0x0002, .platform_mask = 0x20, .driver_data = 0xa0000d1 }, > { ..., .model = 0xad, .steppings = 0x0002, .platform_mask = 0x95, .driver_data = 0x10003a2 }, > > As you can see, this differentiation with platform ID has been > necessary for a long time and is still relevant today. > > Without the platform matching, the old microcode table is incomplete. > For instance, it might lead someone with a Pentium III, platform 0x0, > and microcode 0x40 to think that they should have microcode 0x45, > which is really only for platform 0x4 (.platform_mask==0x08). > > In practice, this meant that folks with fully updated microcode were > seeing "Vulnerable" in the "old_microcode" file. > > 1. https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files > > Signed-off-by: Dave Hansen > Reported-by: Jon Kohler > Fixes: 4e2c719782a8 ("x86/cpu: Help users notice when running old Intel microcode") > Link: https://lore.kernel.org/all/3ECBB974-C6F0-47A7-94B6-3646347F1CC2@nutanix.com/ > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: Borislav Petkov > Cc: Dave Hansen > Cc: "H. Peter Anvin" > Cc: Tony Luck > Cc: Pawan Gupta > Cc: "Peter Zijlstra (Intel)" > Cc: x86@kernel.org > --- > > b/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h | 368 +++++++++++---------- > 1 file changed, 208 insertions(+), 160 deletions(-) Reproduce the issue: On a SPR-SP (F-M-S: 06-8f-08) machine, update the microcode to the latest 20251111 release: * v6.19.0-rc6 (w/o this series): # dmesg | grep microcode [    0.000000] x86/CPU: Running old microcode [   20.400144] microcode: Current revision: 0x2b000650 [   20.408038] microcode: Updated early from: 0x2b000461 * v6.19.0-rc6 (with this series): # dmesg | grep microcode [   20.499999] microcode: Current revision: 0x2b000650 [   20.507562] microcode: Updated early from: 0x2b000461 The false positive complain about old microcode is fixed on my machine. So, Tested-by: Zhao Liu