From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB99A366DD6 for ; Tue, 20 Jan 2026 13:56:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768917420; cv=none; b=fStWqV5ZVTVc6Zzs+aGEAE17krJWK10SFkZ57rLZ2HEFFvTRhuZacKULZLRRC5GaCCIbyJhkNHx4DaOWiEiYSlC71lZwgWDMQfjITWpYZkxy5ZrfGeStPVwGTLW8XbzKMQ/mZcBeQWneN/QbcIraiVAbZFhqcjZMRsugvHgPdWE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768917420; c=relaxed/simple; bh=Oz2PS8PFD1LDmr8ymNaHAXqQ81E0n1daYb0OyeLdPfU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hn+cqPAng3OOEJ9rIeWVEzJAcxtsnhA1RxZ+DmfUHHTkET7OeYVL07A2pqEJBnpQYdLMwBfjCtTQTTcKZDulnJ2QKM5ToxdeLlSoZle6SUo66HleuSEDEfweK+SOPvYOgDTO7UASg09ZqYdlHRb0g4ZAkdYPpg/N/b3Xs9igoYE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=K1YAluve; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="K1YAluve" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-b7ffbf4284dso693908566b.3 for ; Tue, 20 Jan 2026 05:56:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1768917417; x=1769522217; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=PihClK+bT+Z9Jovg1xgOdZAfgKRFBVik/JXwiYidYiY=; b=K1YAluvex7C3VPvIGu/Y3kBZnveG3pcvRjkjEY45hTlkxf/U7IvQOjQ7x1r6lKn8Wx 2u2av8WV/4eLak4oat7Nc0bN9RWCgGa+sqyXu5lbw/6GMkRtL3VavrtoA5g3SWVVs9Jh c0/d1B7hUJk7GXIAI/YYQ+4t0IZGTWwrxLWG8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768917417; x=1769522217; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PihClK+bT+Z9Jovg1xgOdZAfgKRFBVik/JXwiYidYiY=; b=axg4EfhQy6+OHlZUtE3Ikc+eaWBwxBbQ01JcR8lhWu2CIfwzx6KObWeHOL7/1EtghU ihPQZh3+aNUfuXwJ9AfjSGYJ4YR/aDosnIvegA2+14FfTyABGlbE87p1WvLQ893659p4 fm8Es4V/MGR37vcH/5ue+e6jyhmSyZKXTrrU7TNn1b0Wa3hLAuEDst8b9XhbQgOYqVGN z2DziuXE+ge7s7rBFzJCF/ox1wKL2XdobF+FzFNOWq6X/goYc0qfyUXEAaW03guokToe IfwFASK6L42erXF0ISLT6rlpF0492Ay/4Z4RBopRhOE2pD2jBLXWXtzdGnFLUC+GTF0R RoMA== X-Forwarded-Encrypted: i=1; AJvYcCUwbqTkeZcSCS0cqLOhl1a9jNtUdeBLD2ULcgXv5pVeyZZTfP86SNUq2pdq8ZOpiTMVn+gevimuGRgE868=@vger.kernel.org X-Gm-Message-State: AOJu0YyxQ+tW7VKbEkmc3DUpeCzIfrM1Ti6IXvQDqzNkmBBwPbhMJ936 3yO5HTuVAlMnzBpiD4HS4sMGhuWbpsVCumO0N9/i6a3EiWj533dncqnNVWDxXiSvgQ== X-Gm-Gg: AZuq6aKOGksesq5tnGLEa4bLmdOr9e66R0per4Dl00rfbqdQMEf3hXAE4o32JwLcC42 tQAHsnauITwzfmfzV6Bjq0bO8JOw2mt7DMXfepzC99ymuDeCN1L8r37nJrdGzAszMJTmGGPXi4E 439guPpbO7qDpbzk0on2OxwAoF1Lf2V9eJepy87JdlJf7gcW1w9hzi6tWJBzMMqKv4VhHmO4MkT fXP6lqhmt6iyvNy9MDmqBF1eYm3bMGiEPLZRjXQkzdl06qG6cQj69LtyX8j7OOJQQkx/rLR3xcR 8gng5cRh+OOl8F6SaPzS58ly6vpGLQiT3eS9W+dK6lXcOQGlEHzf/2AwOw8GlYJUK72mnKGTI2S cF0tFFUWpWtfN2XOe+iJGNxpmu3enHG4XzfGHKONzdCfhQ8ceLrqVFuIdnPp3Rsv1Wq5pjyxwq0 FPeW2jiuCorLzcdu8= X-Received: by 2002:a17:907:d7cb:b0:b86:eda4:f770 with SMTP id a640c23a62f3a-b8792e0cda9mr1441703466b.21.1768917417228; Tue, 20 Jan 2026 05:56:57 -0800 (PST) Received: from google.com ([2a02:a31b:20c3:6680:e571:3179:cb1d:9314]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b87959c9f8dsm1393030166b.36.2026.01.20.05.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 05:56:56 -0800 (PST) Date: Tue, 20 Jan 2026 14:56:53 +0100 From: Dmytro Maluka To: Lu Baolu Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma Subject: Re: [PATCH v2 1/3] iommu/vt-d: Clear Present bit before tearing down PASID entry Message-ID: References: <20260120061816.2132558-1-baolu.lu@linux.intel.com> <20260120061816.2132558-2-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260120061816.2132558-2-baolu.lu@linux.intel.com> On Tue, Jan 20, 2026 at 02:18:12PM +0800, Lu Baolu wrote: > The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 > bytes). When tearing down an entry, the current implementation zeros the > entire 64-byte structure immediately using multiple 64-bit writes. > > Since the IOMMU hardware may fetch these 64 bytes using multiple > internal transactions (e.g., four 128-bit bursts), updating or zeroing > the entire entry while it is active (P=1) risks a "torn" read. If a > hardware fetch occurs simultaneously with the CPU zeroing the entry, the > hardware could observe an inconsistent state, leading to unpredictable > behavior or spurious faults. > > Follow the "Guidance to Software for Invalidations" in the VT-d spec > (Section 6.5.3.3) by implementing the recommended ownership handshake: > > 1. Clear only the 'Present' (P) bit of the PASID entry. > 2. Use a dma_wmb() to ensure the cleared bit is visible to hardware > before proceeding. > 3. Execute the required invalidation sequence (PASID cache, IOTLB, and > Device-TLB flush) to ensure the hardware has released all cached > references. > 4. Only after the flushes are complete, zero out the remaining fields > of the PASID entry. > > Also, add a dma_wmb() in pasid_set_present() to ensure that all other > fields of the PASID entry are visible to the hardware before the Present > bit is set. > > Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables") > Signed-off-by: Lu Baolu Reviewed-by: Dmytro Maluka > --- > drivers/iommu/intel/pasid.h | 14 ++++++++++++++ > drivers/iommu/intel/pasid.c | 6 +++++- > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h > index b4c85242dc79..0b303bd0b0c1 100644 > --- a/drivers/iommu/intel/pasid.h > +++ b/drivers/iommu/intel/pasid.h > @@ -234,9 +234,23 @@ static inline void pasid_set_wpe(struct pasid_entry *pe) > */ > static inline void pasid_set_present(struct pasid_entry *pe) > { > + dma_wmb(); > pasid_set_bits(&pe->val[0], 1 << 0, 1); > } > > +/* > + * Clear the Present (P) bit (bit 0) of a scalable-mode PASID table entry. > + * This initiates the transition of the entry's ownership from hardware > + * to software. The caller is responsible for fulfilling the invalidation > + * handshake recommended by the VT-d spec, Section 6.5.3.3 (Guidance to > + * Software for Invalidations). > + */ > +static inline void pasid_clear_present(struct pasid_entry *pe) > +{ > + pasid_set_bits(&pe->val[0], 1 << 0, 0); > + dma_wmb(); > +} > + > /* > * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID > * entry. > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c > index 3e2255057079..eb069aefa4fa 100644 > --- a/drivers/iommu/intel/pasid.c > +++ b/drivers/iommu/intel/pasid.c > @@ -272,7 +272,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, > > did = pasid_get_domain_id(pte); > pgtt = pasid_pte_get_pgtt(pte); > - intel_pasid_clear_entry(dev, pasid, fault_ignore); > + pasid_clear_present(pte); > spin_unlock(&iommu->lock); > > if (!ecap_coherent(iommu->ecap)) > @@ -286,6 +286,10 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, > iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); > > devtlb_invalidation_with_pasid(iommu, dev, pasid); > + intel_pasid_clear_entry(dev, pasid, fault_ignore); > + if (!ecap_coherent(iommu->ecap)) > + clflush_cache_range(pte, sizeof(*pte)); > + > if (!fault_ignore) > intel_iommu_drain_pasid_prq(dev, pasid); > } > -- > 2.43.0