From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 79C2023F294 for ; Mon, 19 Jan 2026 18:17:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768846654; cv=none; b=MHZd5ff6c0+cYinMruBn541O/rHXLVgXJG9krNwDJUCQ3p1tSRPgxOHm7gEsB//V8HfAAcKotUJ5Qcfvg/3Z7714bvUUYIq/NytqZ1wl51ZEcVKNV4BatlXuzUPhcv46IIjsUR+Kwcbncq95OuJjbGzbtd6tyQ+6YvmUHDtwouw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768846654; c=relaxed/simple; bh=ptYtQdlBiZy6qG2cfut6u9JloDFUXHrR9S6BMYqZHz4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=DJbZlLY3SziLpBjdMdTFT6VVPsHNCJ8zMfES7McR+H5ZJ9XaIx7Tz+XoHHY4KVHrt/vB6+r4hlR+8AGFL9574eXz5v6IucIHi5q0auVThTWxa2rMagrIofxUw7kqS1sCQ9H3ZRbOCSP/PNY5gujrOuJsvRcY3yr/V37++CCXnVU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39BBC497; Mon, 19 Jan 2026 10:17:25 -0800 (PST) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F222A3F694; Mon, 19 Jan 2026 10:17:30 -0800 (PST) Date: Mon, 19 Jan 2026 18:17:28 +0000 From: Catalin Marinas To: Carl Worth Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Taehyun Noh , Peter Collingbourne Subject: Re: [PATCH v2 1/2] arm64: mte: Clarify kernel MTE policy and manipulation of TCO Message-ID: References: <20251030-mte-tighten-tco-v2-0-e259dda9d5b3@os.amperecomputing.com> <20251030-mte-tighten-tco-v2-1-e259dda9d5b3@os.amperecomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251030-mte-tighten-tco-v2-1-e259dda9d5b3@os.amperecomputing.com> + Peter as he contributed the original patch for skipping PSTATE.TCO clearing. On Thu, Jan 15, 2026 at 03:07:17PM -0800, Carl Worth wrote: > From: Taehyun Noh > > The kernel's primary knob for controlling MTE tag checking is the > PSTATE.TCO bit (tag check override). TCO is enabled (which, > confusingly _disables_ tag checking) by the hardware at the time of an > exception. Then, at various times, when the kernel needs to enable > tag-checking it clears TCO, (which in turn allows TCF0 or TCF to > control whether tag-checking occurs). > > Some of the TCO manipulation code is unclear or perhaps confusing. > > Make the code more clear by introducing a new function > user_uses_tagcheck which captures the existing condition for testing > whether tag checking is desired. This new function includes > significant new comments to help explain the logic. > > Also fix the confusing naming by renaming mte_disable_tco_entry() to > set_kernel_mte_policy(). This function does not necessarily disable > TCO, but does so only conditionally in the case of KASAN HW TAGS. The > new name accurately describes the purpose of the function. > > This commit should have no behavioral change. > > Signed-off-by: Taehyun Noh > Co-developed-by: Carl Worth > Signed-off-by: Carl Worth > --- > arch/arm64/include/asm/mte.h | 40 +++++++++++++++++++++++++++++++++------- > arch/arm64/kernel/entry-common.c | 4 ++-- > arch/arm64/kernel/mte.c | 2 +- > 3 files changed, 36 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h > index 6d4a78b9dc3e..fccb51b2abb0 100644 > --- a/arch/arm64/include/asm/mte.h > +++ b/arch/arm64/include/asm/mte.h > @@ -224,7 +224,35 @@ static inline bool folio_try_hugetlb_mte_tagging(struct folio *folio) > } > #endif > > -static inline void mte_disable_tco_entry(struct task_struct *task) > +static inline bool user_uses_tagcheck(struct task_struct *task) The naming is not entirely correct since the user may have enabled asynchronous tag checks. They are still checks. > +{ > + /* > + * To decide whether userspace wants tag checking we only look > + * at TCF0 (SCTLR_EL1.TCF0 bit 0 is set for both synchronous > + * or asymmetric mode). > + * > + * There's an argument that could be made that the kernel > + * should also consider the state of TCO (tag check override) > + * since userspace does have the ability to set that as well, > + * and that could suggest a desire to disable tag checking in > + * spite of the state of TCF0. However, the Linux kernel has > + * never historically considered the userspace state of TCO, > + * (so changing this would be an ABI break), and the hardware > + * unconditionally sets TCO when an exception occurs > + * anyway. This behaviour around user TCO is already documented in Documentation/arch/arm64/memory-tagging-extension.rst. > + * > + * So, again, here we look only at TCF0 and do not consider > + * TCO. > + */ > + return (task->thread.sctlr_user & (1UL << SCTLR_EL1_TCF0_SHIFT)); > +} > + > +/* > + * Set the kernel's desired policy for MTE tag checking. > + * > + * This function should be used right after the kernel entry. > + */ > +static inline void set_kernel_mte_policy(struct task_struct *task) > { > if (!system_supports_mte()) > return; > @@ -232,15 +260,13 @@ static inline void mte_disable_tco_entry(struct task_struct *task) > /* > * Re-enable tag checking (TCO set on exception entry). This is only > * necessary if MTE is enabled in either the kernel or the userspace > - * task in synchronous or asymmetric mode (SCTLR_EL1.TCF0 bit 0 is set > - * for both). With MTE disabled in the kernel and disabled or > - * asynchronous in userspace, tag check faults (including in uaccesses) > - * are not reported, therefore there is no need to re-enable checking. > + * task. With MTE disabled in the kernel and disabled or asynchronous > + * in userspace, tag check faults (including in uaccesses) are not > + * reported, therefore there is no need to re-enable checking. > * This is beneficial on microarchitectures where re-enabling TCO is > * expensive. > */ > - if (kasan_hw_tags_enabled() || > - (task->thread.sctlr_user & (1UL << SCTLR_EL1_TCF0_SHIFT))) > + if (kasan_hw_tags_enabled() || user_uses_tagcheck(task)) > asm volatile(SET_PSTATE_TCO(0)); > } TBH, I'm fine with leaving the logic in this function without introducing a new user_uses_tagcheck() but not strongly opposed to it with better naming. That said, the set_kernel_mte_policy() naming looks too broad. The policy somehow implies tag check mode, fault behaviour. All it does is dealing with PSTATE.TCO. -- Catalin