From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C6BB832AABF for ; Mon, 19 Jan 2026 17:57:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768845478; cv=none; b=OLG2VNpLb440wgPh9cQ3gJadLr+VaxW7N3Gvw/dIt/j50QVJvG2H9M0LcRncNgYlFYcC6q70oancSHGqzlE5868nHmQOhi+dxWqkUrRrvTH+Rmark2s9TQrlDbeMmtYkPLi7Ff+uf/Gvhj0pphBfYOwA5zkLnwNvjBizA55ukkE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768845478; c=relaxed/simple; bh=o03V7OsRgK8k+AtaktZDDsR3X3M3VhuS4hNXrmNU+nY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GGkUFRMZiTN35QBctgd54MlWbSAnPPaihncaRHE8n3a3tfZIVW4AYUx+11HB3mKeW0oMWMXiG7UH47Lw7kkbm/eC6WsAEzWdc/qAqlQnOfOFoBicrw16VP03mqre2CQt17lXY3qHehnEaWSMEH4hi1U6Cx6NhqXTo8im66bYK2k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A5E6497; Mon, 19 Jan 2026 09:57:48 -0800 (PST) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4A3333F694; Mon, 19 Jan 2026 09:57:54 -0800 (PST) Date: Mon, 19 Jan 2026 17:57:51 +0000 From: Catalin Marinas To: Carl Worth Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Taehyun Noh Subject: Re: [PATCH v2 2/2] arm64: mte: Set TCMA1 whenever MTE is present in the kernel Message-ID: References: <20251030-mte-tighten-tco-v2-0-e259dda9d5b3@os.amperecomputing.com> <20251030-mte-tighten-tco-v2-2-e259dda9d5b3@os.amperecomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251030-mte-tighten-tco-v2-2-e259dda9d5b3@os.amperecomputing.com> On Thu, Jan 15, 2026 at 03:07:18PM -0800, Carl Worth wrote: > Set the TCMA1 bit so that access to TTBR1 addresses with 0xf in their > tag bits will be treated as tag unchecked. > > This is important to avoid unwanted tag checking on some > systems. Specifically, SCTLR_EL1.TCF can be set to indicate that no > tag check faults are desired. But the architecture doesn't guarantee > that in this case the system won't still perform tag checks. > > Use TCMA1 to ensure that undesired tag checks are not performed. This > bit was already set in the KASAN case. Adding it to the non-KASAN case > prevents tag checking since all TTBR1 address will have a value of 0xf > in their tag bits. > > This patch has been measured on an Ampere system to improve the following: > > * Eliminate over 98% of kernel-side tag checks during "perf bench > futex hash", as measured with "perf stat". > > * Eliminate all MTE overhead (was previously a 25% performance > penalty) from the Phoronix pts/memcached benchmark (1:10 Set:Get > ration with 96 cores). > > Reported-by: Taehyun Noh > Suggested-by: Catalin Marinas > Signed-off-by: Carl Worth Thanks for testing an sending this. Reviewed-by: Catalin Marinas