From: Sergey Matyukevich <geomatsi@gmail.com>
To: Andy Chiu <andybnac@gmail.com>, Paul Walmsley <pjw@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-kselftest@vger.kernel.org, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Oleg Nesterov <oleg@redhat.com>,
Shuah Khan <shuah@kernel.org>, Thomas Huth <thuth@redhat.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Samuel Holland <samuel.holland@sifive.com>,
Joel Granados <joel.granados@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Yong-Xuan Wang <yongxuan.wang@sifive.com>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>
Subject: Re: [PATCH v5 2/9] riscv: vector: init vector context with proper vlenb
Date: Mon, 19 Jan 2026 23:48:21 +0300 [thread overview]
Message-ID: <aW6YlXEbusvDiDWw@curiosity> (raw)
In-Reply-To: <CAFTtA3MdoL5XjcjTrNhZ27UXZe4Mxot-rttc8cQ-K=E-Mh164A@mail.gmail.com>
Hi,
On Wed, Jan 07, 2026 at 12:49:31AM -0600, Andy Chiu wrote:
> On Sun, Dec 14, 2025 at 10:35 AM Sergey Matyukevich <geomatsi@gmail.com> wrote:
> >
> > The vstate in thread_struct is zeroed when the vector context is
> > initialized. That includes read-only register vlenb, which holds
> > the vector register length in bytes. Zeroed state persists until
> > mstatus.VS becomes 'dirty' and a context switch saves the actual
> > hardware values.
> >
> > This can expose the zero vlenb value to the user-space in early
> > debug scenarios, e.g. when ptrace attaches to a traced process
> > early, before any vector instruction except the first one was
> > executed.
> >
> > Fix this by specifying proper vlenb on vector context init.
> >
> > Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
>
> Reviewed-by: Andy Chiu <andybnac@gmail.com>
>
Thanks for reviews !
What would be the recommended way to proceed with these patches ?
I have reviews from Andy for the patches 1,2 and 5 (selftest for 2).
They can be used independently of the remainig ptrace v-state
validation changes and their tests.
Would it make sense to split the series into two parts, so that
the v-state validation can continue evolve independently ?
Regards,
Sergey
next prev parent reply other threads:[~2026-01-19 20:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-14 16:35 [PATCH v5 0/9] riscv: vector: misc ptrace fixes for debug use-cases Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 1/9] riscv: ptrace: return ENODATA for inactive vector extension Sergey Matyukevich
2026-01-07 6:48 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 2/9] riscv: vector: init vector context with proper vlenb Sergey Matyukevich
2026-01-07 6:49 ` Andy Chiu
2026-01-19 20:48 ` Sergey Matyukevich [this message]
2025-12-14 16:35 ` [PATCH v5 3/9] riscv: csr: define vtype register elements Sergey Matyukevich
2026-01-21 21:04 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 4/9] riscv: ptrace: validate input vector csr registers Sergey Matyukevich
2026-01-21 21:07 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 5/9] selftests: riscv: test ptrace vector interface Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 6/9] selftests: riscv: verify initial vector state with ptrace Sergey Matyukevich
2026-01-21 21:33 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 7/9] selftests: riscv: verify syscalls discard vector context Sergey Matyukevich
2026-01-21 21:37 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 8/9] selftests: riscv: verify ptrace rejects invalid vector csr inputs Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 9/9] selftests: riscv: verify ptrace accepts valid vector csr values Sergey Matyukevich
2026-01-21 21:47 ` [PATCH v5 0/9] riscv: vector: misc ptrace fixes for debug use-cases Andy Chiu
2026-01-24 8:30 ` patchwork-bot+linux-riscv
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