From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
tomm.merciai@gmail.com, linux-renesas-soc@vger.kernel.org,
biju.das.jz@bp.renesas.com,
Andrzej Hajda <andrzej.hajda@intel.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Robert Foss <rfoss@kernel.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Magnus Damm <magnus.damm@gmail.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 09/22] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/G3E SoC
Date: Fri, 9 Jan 2026 18:36:10 +0100 [thread overview]
Message-ID: <aWE8ikhsthB_0VQV@tom-desktop> (raw)
In-Reply-To: <CAMuHMdUm-yHkRw0k42pfq9BD8urLO7rqF2yD7s2JbkMFpRTQwQ@mail.gmail.com>
Hi Geert,
Thanks for your comment!
On Fri, Jan 09, 2026 at 05:22:02PM +0100, Geert Uytterhoeven wrote:
> Hi Tommaso,
>
> On Fri, 9 Jan 2026 at 17:06, Tommaso Merciai
> <tommaso.merciai.xr@bp.renesas.com> wrote:
> > On Sun, Nov 30, 2025 at 09:24:57AM +0100, Krzysztof Kozlowski wrote:
> > > On 26/11/2025 15:07, Tommaso Merciai wrote:
> > > > The MIPI DSI interface on the RZ/G3E SoC is nearly identical to that of
> > > > the RZ/V2H(P) SoC, except that this have 2 input port and can use vclk1
> > > > or vclk2 as DSI Video clock, depending on the selected port.
> > > >
> > > > To accommodate these differences, a SoC-specific
> > > > `renesas,r9a09g047-mipi-dsi` compatible string has been added for the
> > > > RZ/G3E SoC.
> > > >
> > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > > > ---
> > > > .../bindings/display/bridge/renesas,dsi.yaml | 120 +++++++++++++++---
> > > > 1 file changed, 101 insertions(+), 19 deletions(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > > > index c20625b8425e..9917b494a9c9 100644
> > > > --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > > > @@ -28,6 +28,7 @@ properties:
> > > > - const: renesas,r9a09g057-mipi-dsi
> > > >
> > > > - enum:
> > > > + - renesas,r9a09g047-mipi-dsi # RZ/G3E
> > > > - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
> > > >
> > > > reg:
> > > > @@ -84,6 +85,13 @@ properties:
> > > > - const: pclk
> > > > - const: vclk
> > > > - const: lpclk
> > > > + - items:
> > > > + - const: pllrefclk
> > > > + - const: aclk
> > > > + - const: pclk
> > > > + - const: vclk1
> > > > + - const: vclk2
> > > > + - const: lpclk
> > >
> > > Why are you creating completely new lists every time?
> > >
> > > No, come with unified approach.
> >
> > The intent is not to create a completely new clock list per IP, but to keep a
> > unified clock definition that can scale with feature differences.
> >
> > The previous IP supports a single DSI input port, whereas this IP supports two
> > DSI input ports.
> >
> > Because of this added capability, the hardware naturally introduced an
> > additional clock.
> >
> > Can you please suggest how to handle it?
>
> Keep on calling the first vclk "vclk", and add "vclk2" at the end of the list?
> Then RZ/V2H can specify the first 5 clocks, and RZ/G3E can specify all 6.
Testing a bit your suggestion
we can do:
clock-names:
oneOf:
- items:
- const: pllclk
- const: sysclk
- const: aclk
- const: pclk
- const: vclk
- const: lpclk
- minItems: 5
items:
- const: pllrefclk
- const: aclk
- const: pclk
- const: vclk
- const: lpclk
- const: vclk2
Then later into the compatible if switch we can do:
- if:
properties:
compatible:
contains:
const: renesas,r9a09g047-mipi-dsi
then:
properties:
clocks:
items:
- description: DSI PLL reference input clock
- description: DSI AXI bus clock
- description: DSI Register access clock
- description: DSI Video clock
- description: DSI D-PHY Escape mode transmit clock
- description: DSI Video clock (2nd input clock)
clock-names:
minItems: 6
Thanks & Regards,
Tommaso
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
next prev parent reply other threads:[~2026-01-09 17:36 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-26 14:07 [PATCH 00/22] Add support for DU and DSI on the Renesas RZ/G3E SoC Tommaso Merciai
2025-11-26 14:07 ` [PATCH 01/22] clk: renesas: rzv2h: Add PLLDSI clk mux support Tommaso Merciai
2026-01-09 18:27 ` Geert Uytterhoeven
2026-01-12 8:12 ` Tommaso Merciai
2026-01-14 13:07 ` Geert Uytterhoeven
2026-01-23 15:52 ` Tommaso Merciai
2026-01-14 12:59 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 02/22] clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support Tommaso Merciai
2026-01-09 18:27 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 03/22] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks Tommaso Merciai
2026-01-09 18:35 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 04/22] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks Tommaso Merciai
2026-01-09 18:36 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 05/22] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks Tommaso Merciai
2026-01-09 18:37 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 06/22] clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK Tommaso Merciai
2026-01-09 18:38 ` Geert Uytterhoeven
2026-01-13 13:51 ` Tommaso Merciai
2025-11-26 14:07 ` [PATCH 07/22] clk: renesas: r9a09g047: Add support for DSI clocks and resets Tommaso Merciai
2026-01-09 18:39 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 08/22] clk: renesas: r9a09g047: Add support for LCDC{0,1} " Tommaso Merciai
2026-01-09 18:39 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 09/22] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/G3E SoC Tommaso Merciai
2025-11-30 8:24 ` Krzysztof Kozlowski
2026-01-09 16:06 ` Tommaso Merciai
2026-01-09 16:22 ` Geert Uytterhoeven
2026-01-09 17:36 ` Tommaso Merciai [this message]
2026-01-09 17:59 ` Geert Uytterhoeven
2026-01-12 11:17 ` Tommaso Merciai
2026-01-12 11:35 ` Geert Uytterhoeven
2026-01-12 11:59 ` Tommaso Merciai
2026-01-12 13:33 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 10/22] dt-bindings: display: renesas,rzg2l-du: " Tommaso Merciai
2025-12-03 8:23 ` Krzysztof Kozlowski
2025-12-03 13:41 ` Tommaso Merciai
2026-01-14 12:37 ` Geert Uytterhoeven
2026-01-15 7:48 ` Biju Das
2026-01-15 8:24 ` Geert Uytterhoeven
2026-01-15 10:10 ` Biju Das
2026-01-15 10:22 ` Geert Uytterhoeven
2026-01-15 10:34 ` Biju Das
2026-01-15 10:51 ` Geert Uytterhoeven
2026-01-09 15:59 ` Tommaso Merciai
2025-11-26 14:07 ` [PATCH 11/22] drm: renesas: rz-du: mipi_dsi: Add out_port to OF data Tommaso Merciai
2025-11-26 14:07 ` [PATCH 12/22] drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature Tommaso Merciai
2025-11-26 14:07 ` [PATCH 13/22] drm: renesas: rz-du: mipi_dsi: Add support for RZ/G3E Tommaso Merciai
2025-11-26 14:07 ` [PATCH 14/22] drm: renesas: rz-du: Add RZ/G3E support Tommaso Merciai
2026-01-14 9:58 ` Tommaso Merciai
2025-11-26 14:07 ` [PATCH 15/22] media: dt-bindings: media: renesas,vsp1: Document RZ/G3E Tommaso Merciai
2025-12-03 8:25 ` Krzysztof Kozlowski
2026-01-14 15:10 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 16/22] media: dt-bindings: media: renesas,fcp: Document RZ/G3E SoC Tommaso Merciai
2025-12-03 8:26 ` Krzysztof Kozlowski
2026-01-14 15:11 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 17/22] arm64: dts: renesas: r9a09g047: Add fcpvd0 node Tommaso Merciai
2026-01-14 15:12 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 18/22] arm64: dts: renesas: r9a09g047: Add vspd0 node Tommaso Merciai
2026-01-14 15:15 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 19/22] arm64: dts: renesas: r9a09g047: Add fcpvd1 node Tommaso Merciai
2026-01-14 15:14 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 20/22] arm64: dts: renesas: r9a09g047: Add vspd1 node Tommaso Merciai
2026-01-14 15:16 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 21/22] arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes Tommaso Merciai
2026-01-14 15:23 ` Geert Uytterhoeven
2025-11-26 14:07 ` [PATCH 22/22] arm64: dts: renesas: r9a09g047e57-smarc: Enable DU1 and DSI support Tommaso Merciai
2025-11-29 15:33 ` [PATCH 00/22] Add support for DU and DSI on the Renesas RZ/G3E SoC Biju Das
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