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Tue, 13 Jan 2026 11:34:47 -0800 (PST) Received: from google.com ([2a00:79e0:a:200:e42d:53cb:2a0f:636a]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-351067d39b4sm310155a91.0.2026.01.13.11.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 11:34:46 -0800 (PST) Date: Tue, 13 Jan 2026 20:34:40 +0100 From: Dmytro Maluka To: Lu Baolu Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, "Vineeth Pillai (Google)" , Aashish Sharma Subject: Re: [PATCH 2/3] iommu/vt-d: Clear Present bit before tearing down PASID entry Message-ID: References: <20260113030052.977366-1-baolu.lu@linux.intel.com> <20260113030052.977366-3-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260113030052.977366-3-baolu.lu@linux.intel.com> On Tue, Jan 13, 2026 at 11:00:47AM +0800, Lu Baolu wrote: > The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 > bytes). When tearing down an entry, the current implementation zeros the > entire 64-byte structure immediately. > > However, the IOMMU hardware may fetch these 64 bytes using multiple > internal transactions (e.g., four 128-bit bursts). If a hardware fetch > occurs simultaneously with the CPU zeroing the entry, the hardware could > observe a "torn" entry — where some chunks are zeroed and others still > contain old data — leading to unpredictable behavior or spurious faults. > > Follow the "Guidance to Software for Invalidations" in the VT-d spec > (Section 6.5.3.3) by implementing a proper ownership handshake: > > 1. Clear only the 'Present' (P) bit of the PASID entry. This tells the > hardware that the entry is no longer valid. > 2. Execute the required invalidation sequence (PASID cache, IOTLB, and > Device-TLB flush) to ensure the hardware has released all cached > references to the entry. > 3. Only after the flushes are complete, zero out the remaining fields of > the PASID entry. > > Additionally, add an explicit clflush in intel_pasid_clear_entry() to > ensure that the cleared entry is visible to the IOMMU on systems where > memory coherency (ecap_coherent) is not supported. > > Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables") > Signed-off-by: Lu Baolu > --- > drivers/iommu/intel/pasid.h | 12 ++++++++++++ > drivers/iommu/intel/pasid.c | 9 +++++++-- > 2 files changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h > index b4c85242dc79..35de1d77355f 100644 > --- a/drivers/iommu/intel/pasid.h > +++ b/drivers/iommu/intel/pasid.h > @@ -237,6 +237,18 @@ static inline void pasid_set_present(struct pasid_entry *pe) > pasid_set_bits(&pe->val[0], 1 << 0, 1); > } > > +/* > + * Clear the Present (P) bit (bit 0) of a scalable-mode PASID table entry. > + * This initiates the transition of the entry's ownership from hardware > + * to software. The caller is responsible for fulfilling the invalidation > + * handshake recommended by the VT-d spec, Section 6.5.3.3 (Guidance to > + * Software for Invalidations). > + */ > +static inline void pasid_clear_present(struct pasid_entry *pe) > +{ > + pasid_set_bits(&pe->val[0], 1 << 0, 0); > +} > + > /* > * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID > * entry. > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c > index 298a39183996..4f36138448d8 100644 > --- a/drivers/iommu/intel/pasid.c > +++ b/drivers/iommu/intel/pasid.c > @@ -178,7 +178,8 @@ static struct pasid_entry *intel_pasid_get_entry(struct device *dev, u32 pasid) > * Interfaces for PASID table entry manipulation: > */ > static void > -intel_pasid_clear_entry(struct device *dev, u32 pasid, bool fault_ignore) > +intel_pasid_clear_entry(struct intel_iommu *iommu, struct device *dev, > + u32 pasid, bool fault_ignore) > { > struct pasid_entry *pe; > > @@ -190,6 +191,9 @@ intel_pasid_clear_entry(struct device *dev, u32 pasid, bool fault_ignore) > pasid_clear_entry_with_fpd(pe); > else > pasid_clear_entry(pe); > + > + if (!ecap_coherent(iommu->ecap)) > + clflush_cache_range(pe, sizeof(*pe)); > } > > static void > @@ -272,7 +276,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, > > did = pasid_get_domain_id(pte); > pgtt = pasid_pte_get_pgtt(pte); > - intel_pasid_clear_entry(dev, pasid, fault_ignore); > + pasid_clear_present(pte); > spin_unlock(&iommu->lock); > > if (!ecap_coherent(iommu->ecap)) > @@ -286,6 +290,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, > iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); > > devtlb_invalidation_with_pasid(iommu, dev, pasid); > + intel_pasid_clear_entry(iommu, dev, pasid, fault_ignore); Is it safe to do this with iommu->lock already unlocked? > if (!fault_ignore) > intel_iommu_drain_pasid_prq(dev, pasid); > } > -- > 2.43.0 >