[PATCH v2 0/4 RESEND] gpu/drm: tegra: add DSI support for Tegra20/Tegra30

[PATCH v2 0/4 RESEND] gpu/drm: tegra: add DSI support for Tegra20/Tegra30

[Svyatoslav Ryhel]

Tegra20/Tegra30 DSI is quite similar to Tegra114+ apart MIPI calibration
logic and clocks. With a few minor tweaks, existing tegra DSI driver
should work on Tegra20/Tegra30 devices just fine. Tested on
Motorola Atrix 4G (T20) and ASUS VivoTab RT TF600T (T30).

This patchset depends on Tegra20/Tegra30 CSI bringup since both share
MIPI calibration logic. Ideally these patches should be picked after
CSI bringup but they will not break anything even if picked before
CSI patches.

---
Changes in v2:
- removed all MIPI calibration, it is handled within CSI bringup
- added per-soc structures into of_match
- added fix for hang caused by register access with uninited hw
---

Svyatoslav Ryhel (4):
  clk: tegra20: reparent dsi clock to pll_d_out0
  gpu/drm: tegra: dsi: move prepare function at the top of encoder
    enable
  gpu/drm: tegra: dsi: add support for Tegra20/Tegra30
  ARM: tegra: adjust DSI nodes for Tegra20/Tegra30

 arch/arm/boot/dts/nvidia/tegra20.dtsi |   4 ++
 arch/arm/boot/dts/nvidia/tegra30.dtsi |   8 +++
 drivers/clk/tegra/clk-tegra20.c       |   6 +-
 drivers/gpu/drm/tegra/drm.c           |   2 +
 drivers/gpu/drm/tegra/dsi.c           | 100 ++++++++++++++++----------
 drivers/gpu/drm/tegra/dsi.h           |  15 ++++
 6 files changed, 95 insertions(+), 40 deletions(-)

-- 
2.48.1

[PATCH v2 1/4 RESEND] clk: tegra20: reparent dsi clock to pll_d_out0

[Svyatoslav Ryhel]

Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/tegra/clk-tegra20.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf9a9f8ddf62..9160f27a6cf0 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -801,9 +801,9 @@ static void __init tegra20_periph_clk_init(void)
 	clks[TEGRA20_CLK_MC] = clk;
 
 	/* dsi */
-	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
-				    48, periph_clk_enb_refcnt);
-	clk_register_clkdev(clk, NULL, "dsi");
+	clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0,
+					     clk_base, 0, TEGRA20_CLK_DSI,
+					     periph_clk_enb_refcnt);
 	clks[TEGRA20_CLK_DSI] = clk;
 
 	/* csus */
-- 
2.48.1

Re: [PATCH v2 1/4 RESEND] clk: tegra20: reparent dsi clock to pll_d_out0

[Mikko Perttunen]

On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index bf9a9f8ddf62..9160f27a6cf0 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -801,9 +801,9 @@ static void __init tegra20_periph_clk_init(void)
>  	clks[TEGRA20_CLK_MC] = clk;
>  
>  	/* dsi */
> -	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
> -				    48, periph_clk_enb_refcnt);
> -	clk_register_clkdev(clk, NULL, "dsi");
> +	clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0,
> +					     clk_base, 0, TEGRA20_CLK_DSI,
> +					     periph_clk_enb_refcnt);
>  	clks[TEGRA20_CLK_DSI] = clk;
>  
>  	/* csus */
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v2 1/4 RESEND] clk: tegra20: reparent dsi clock to pll_d_out0

[Thierry Reding]

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On Thu, Dec 04, 2025 at 08:17:00AM +0200, Svyatoslav Ryhel wrote:
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied, thanks.

Thierry

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[PATCH v2 2/4 RESEND] gpu/drm: tegra: dsi: move prepare function to the top of encoder enable

[Svyatoslav Ryhel]

The tegra_dsi_prepare function performs hardware setup and should be
called before any register readings or there will be a risk of device
hangup on register access. To avoid this situation, tegra_dsi_prepare must
be called at the beginning of tegra_dsi_encoder_enable.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/gpu/drm/tegra/dsi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 278bf2c85524..8e80c7efe8b4 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -914,6 +914,12 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
 	u32 value;
 	int err;
 
+	err = tegra_dsi_prepare(dsi);
+	if (err < 0) {
+		dev_err(dsi->dev, "failed to prepare: %d\n", err);
+		return;
+	}
+
 	/* If the bootloader enabled DSI it needs to be disabled
 	 * in order for the panel initialization commands to be
 	 * properly sent.
@@ -923,12 +929,6 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
 	if (value & DSI_POWER_CONTROL_ENABLE)
 		tegra_dsi_disable(dsi);
 
-	err = tegra_dsi_prepare(dsi);
-	if (err < 0) {
-		dev_err(dsi->dev, "failed to prepare: %d\n", err);
-		return;
-	}
-
 	state = tegra_dsi_get_state(dsi);
 
 	tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
-- 
2.48.1

Re: [PATCH v2 2/4 RESEND] gpu/drm: tegra: dsi: move prepare function to the top of encoder enable

[Mikko Perttunen]

On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> The tegra_dsi_prepare function performs hardware setup and should be
> called before any register readings or there will be a risk of device
> hangup on register access. To avoid this situation, tegra_dsi_prepare must
> be called at the beginning of tegra_dsi_encoder_enable.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/gpu/drm/tegra/dsi.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> index 278bf2c85524..8e80c7efe8b4 100644
> --- a/drivers/gpu/drm/tegra/dsi.c
> +++ b/drivers/gpu/drm/tegra/dsi.c
> @@ -914,6 +914,12 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
>  	u32 value;
>  	int err;
>  
> +	err = tegra_dsi_prepare(dsi);
> +	if (err < 0) {
> +		dev_err(dsi->dev, "failed to prepare: %d\n", err);
> +		return;
> +	}
> +
>  	/* If the bootloader enabled DSI it needs to be disabled
>  	 * in order for the panel initialization commands to be
>  	 * properly sent.
> @@ -923,12 +929,6 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
>  	if (value & DSI_POWER_CONTROL_ENABLE)
>  		tegra_dsi_disable(dsi);
>  
> -	err = tegra_dsi_prepare(dsi);
> -	if (err < 0) {
> -		dev_err(dsi->dev, "failed to prepare: %d\n", err);
> -		return;
> -	}
> -
>  	state = tegra_dsi_get_state(dsi);
>  
>  	tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
> 

The section of code before the tegra_dsi_prepare call was removed in 'Revert "drm/tegra: dsi: Clear enable register if powered by bootloader"', so this patch should no longer be necessary.

Mikko

Re: [PATCH v2 2/4 RESEND] gpu/drm: tegra: dsi: move prepare function to the top of encoder enable

[Svyatoslav Ryhel]

чт, 15 січ. 2026 р. о 07:54 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> > The tegra_dsi_prepare function performs hardware setup and should be
> > called before any register readings or there will be a risk of device
> > hangup on register access. To avoid this situation, tegra_dsi_prepare must
> > be called at the beginning of tegra_dsi_encoder_enable.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  drivers/gpu/drm/tegra/dsi.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> > index 278bf2c85524..8e80c7efe8b4 100644
> > --- a/drivers/gpu/drm/tegra/dsi.c
> > +++ b/drivers/gpu/drm/tegra/dsi.c
> > @@ -914,6 +914,12 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
> >       u32 value;
> >       int err;
> >
> > +     err = tegra_dsi_prepare(dsi);
> > +     if (err < 0) {
> > +             dev_err(dsi->dev, "failed to prepare: %d\n", err);
> > +             return;
> > +     }
> > +
> >       /* If the bootloader enabled DSI it needs to be disabled
> >        * in order for the panel initialization commands to be
> >        * properly sent.
> > @@ -923,12 +929,6 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
> >       if (value & DSI_POWER_CONTROL_ENABLE)
> >               tegra_dsi_disable(dsi);
> >
> > -     err = tegra_dsi_prepare(dsi);
> > -     if (err < 0) {
> > -             dev_err(dsi->dev, "failed to prepare: %d\n", err);
> > -             return;
> > -     }
> > -
> >       state = tegra_dsi_get_state(dsi);
> >
> >       tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
> >
>
> The section of code before the tegra_dsi_prepare call was removed in 'Revert "drm/tegra: dsi: Clear enable register if powered by bootloader"', so this patch should no longer be necessary.
>
> Mikko
>

You are correct. I have found this when rebasing onto v6.18 which was
much later then this series was resent. Obviously, this patch would be
dropped on the next resend/v3. Sorry for inconvenience.

>
>

Re: [PATCH v2 2/4 RESEND] gpu/drm: tegra: dsi: move prepare function to the top of encoder enable

[Svyatoslav Ryhel]

чт, 15 січ. 2026 р. о 09:49 Svyatoslav Ryhel <clamor95@gmail.com> пише:
>
> чт, 15 січ. 2026 р. о 07:54 Mikko Perttunen <mperttunen@nvidia.com> пише:
> >
> > On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> > > The tegra_dsi_prepare function performs hardware setup and should be
> > > called before any register readings or there will be a risk of device
> > > hangup on register access. To avoid this situation, tegra_dsi_prepare must
> > > be called at the beginning of tegra_dsi_encoder_enable.
> > >
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > >  drivers/gpu/drm/tegra/dsi.c | 12 ++++++------
> > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> > > index 278bf2c85524..8e80c7efe8b4 100644
> > > --- a/drivers/gpu/drm/tegra/dsi.c
> > > +++ b/drivers/gpu/drm/tegra/dsi.c
> > > @@ -914,6 +914,12 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
> > >       u32 value;
> > >       int err;
> > >
> > > +     err = tegra_dsi_prepare(dsi);
> > > +     if (err < 0) {
> > > +             dev_err(dsi->dev, "failed to prepare: %d\n", err);
> > > +             return;
> > > +     }
> > > +
> > >       /* If the bootloader enabled DSI it needs to be disabled
> > >        * in order for the panel initialization commands to be
> > >        * properly sent.
> > > @@ -923,12 +929,6 @@ static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
> > >       if (value & DSI_POWER_CONTROL_ENABLE)
> > >               tegra_dsi_disable(dsi);
> > >
> > > -     err = tegra_dsi_prepare(dsi);
> > > -     if (err < 0) {
> > > -             dev_err(dsi->dev, "failed to prepare: %d\n", err);
> > > -             return;
> > > -     }
> > > -
> > >       state = tegra_dsi_get_state(dsi);
> > >
> > >       tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
> > >
> >
> > The section of code before the tegra_dsi_prepare call was removed in 'Revert "drm/tegra: dsi: Clear enable register if powered by bootloader"', so this patch should no longer be necessary.
> >
> > Mikko
> >
>
> You are correct. I have found this when rebasing onto v6.18 which was
> much later then this series was resent. Obviously, this patch would be
> dropped on the next resend/v3. Sorry for inconvenience.
>

Actually, "Revert "drm/tegra: dsi: Clear enable register if powered by
bootloader"" causes a  regression for me (DSI on Tegra20 device,
Motorola Atrix 4G). DSI initiated by bootloader will be stuck if not
disabled pre reconfiguration, Dmitry was right by bringing that
change, but he did not take into account that if DSI is accessed from
cold state (not configured by bootloader), device will hang. This
patch addresses this behavior of Dmitry's patch and prevents
regression introduced by reverting it.

> >
> >

[PATCH v2 3/4 RESEND] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30

[Svyatoslav Ryhel]

Tegra20 and Tegra30 are fully compatible with existing tegra DSI driver
apart from clock configuration and PAD calibration which are addressed by
this patch.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/gpu/drm/tegra/drm.c |  2 +
 drivers/gpu/drm/tegra/dsi.c | 88 ++++++++++++++++++++++++-------------
 drivers/gpu/drm/tegra/dsi.h | 15 +++++++
 3 files changed, 74 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 4596073fe28f..5d64cd57e764 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
 
 static const struct of_device_id host1x_drm_subdevs[] = {
 	{ .compatible = "nvidia,tegra20-dc", },
+	{ .compatible = "nvidia,tegra20-dsi", },
 	{ .compatible = "nvidia,tegra20-hdmi", },
 	{ .compatible = "nvidia,tegra20-gr2d", },
 	{ .compatible = "nvidia,tegra20-gr3d", },
 	{ .compatible = "nvidia,tegra30-dc", },
+	{ .compatible = "nvidia,tegra30-dsi", },
 	{ .compatible = "nvidia,tegra30-hdmi", },
 	{ .compatible = "nvidia,tegra30-gr2d", },
 	{ .compatible = "nvidia,tegra30-gr3d", },
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 8e80c7efe8b4..d079aa7d2a85 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -53,6 +53,10 @@ to_dsi_state(struct drm_connector_state *state)
 	return container_of(state, struct tegra_dsi_state, base);
 }
 
+struct tegra_dsi_config {
+	u32 dsi_version;
+};
+
 struct tegra_dsi {
 	struct host1x_client client;
 	struct tegra_output output;
@@ -82,6 +86,8 @@ struct tegra_dsi {
 	/* for ganged-mode support */
 	struct tegra_dsi *master;
 	struct tegra_dsi *slave;
+
+	const struct tegra_dsi_config *config;
 };
 
 static inline struct tegra_dsi *
@@ -663,39 +669,46 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
 {
 	u32 value;
 
-	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
-	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
+	if (dsi->config->dsi_version == TEGRA_DSI_V1) {
+		/*
+		 * XXX Is this still needed? The module reset is deasserted right
+		 * before this function is called.
+		 */
+		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
+		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
+		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
+		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
+		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
+
+		value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
+		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
+
+		value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
+			DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
+			DSI_PAD_OUT_CLK(0x0);
+		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
+
+		value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
+			DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
+		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
+	} else {
+		value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) |
+			DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) |
+			DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) |
+			DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0);
+		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
+	}
 
 	return 0;
 }
 
 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
 {
-	u32 value;
 	int err;
 
-	/*
-	 * XXX Is this still needed? The module reset is deasserted right
-	 * before this function is called.
-	 */
-	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
-	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
-	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
-	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
-	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
-
 	/* start calibration */
 	tegra_dsi_pad_enable(dsi);
 
-	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
-		DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
-		DSI_PAD_OUT_CLK(0x0);
-	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
-
-	value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
-		DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
-	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
-
 	err = tegra_mipi_start_calibration(dsi->mipi);
 	if (err < 0)
 		return err;
@@ -1577,6 +1590,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
 	if (!dsi)
 		return -ENOMEM;
 
+	dsi->config = of_device_get_match_data(&pdev->dev);
 	dsi->output.dev = dsi->dev = &pdev->dev;
 	dsi->video_fifo_depth = 1920;
 	dsi->host_fifo_depth = 64;
@@ -1615,7 +1629,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
 		goto remove;
 	}
 
-	dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
+	dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp");
 	if (IS_ERR(dsi->clk_lp)) {
 		err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
 				    "cannot get low-power clock\n");
@@ -1636,10 +1650,12 @@ static int tegra_dsi_probe(struct platform_device *pdev)
 		goto remove;
 	}
 
-	err = tegra_dsi_setup_clocks(dsi);
-	if (err < 0) {
-		dev_err(&pdev->dev, "cannot setup clocks\n");
-		goto remove;
+	if (dsi->config->dsi_version == TEGRA_DSI_V1) {
+		err = tegra_dsi_setup_clocks(dsi);
+		if (err < 0) {
+			dev_err(&pdev->dev, "cannot setup clocks\n");
+			goto remove;
+		}
 	}
 
 	dsi->regs = devm_platform_ioremap_resource(pdev, 0);
@@ -1703,11 +1719,21 @@ static void tegra_dsi_remove(struct platform_device *pdev)
 	tegra_mipi_free(dsi->mipi);
 }
 
+static const struct tegra_dsi_config tegra20_dsi_config = {
+	.dsi_version = TEGRA_DSI_V0,
+};
+
+static const struct tegra_dsi_config tegra114_dsi_config = {
+	.dsi_version = TEGRA_DSI_V1,
+};
+
 static const struct of_device_id tegra_dsi_of_match[] = {
-	{ .compatible = "nvidia,tegra210-dsi", },
-	{ .compatible = "nvidia,tegra132-dsi", },
-	{ .compatible = "nvidia,tegra124-dsi", },
-	{ .compatible = "nvidia,tegra114-dsi", },
+	{ .compatible = "nvidia,tegra210-dsi", .data = &tegra114_dsi_config },
+	{ .compatible = "nvidia,tegra132-dsi", .data = &tegra114_dsi_config },
+	{ .compatible = "nvidia,tegra124-dsi", .data = &tegra114_dsi_config },
+	{ .compatible = "nvidia,tegra114-dsi", .data = &tegra114_dsi_config },
+	{ .compatible = "nvidia,tegra30-dsi", .data = &tegra20_dsi_config },
+	{ .compatible = "nvidia,tegra20-dsi", .data = &tegra20_dsi_config },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h
index f39594e65e97..5049ec7813c7 100644
--- a/drivers/gpu/drm/tegra/dsi.h
+++ b/drivers/gpu/drm/tegra/dsi.h
@@ -95,6 +95,16 @@
 #define DSI_TALLY_LRX(x)		(((x) & 0xff) <<  8)
 #define DSI_TALLY_HTX(x)		(((x) & 0xff) <<  0)
 #define DSI_PAD_CONTROL_0		0x4b
+/* DSI V0 */
+#define DSI_PAD_CONTROL_PULLDN_ENAB(x)	(((x) & 0x1) << 28)
+#define DSI_PAD_CONTROL_SLEWUPADJ(x)	(((x) & 0x7) << 24)
+#define DSI_PAD_CONTROL_SLEWDNADJ(x)	(((x) & 0x7) << 20)
+#define DSI_PAD_CONTROL_PREEMP_EN(x)	(((x) & 0x1) << 19)
+#define DSI_PAD_CONTROL_PDIO_CLK(x)	(((x) & 0x1) << 18)
+#define DSI_PAD_CONTROL_PDIO(x)		(((x) & 0x3) << 16)
+#define DSI_PAD_CONTROL_LPUPADJ(x)	(((x) & 0x3) << 14)
+#define DSI_PAD_CONTROL_LPDNADJ(x)	(((x) & 0x3) << 12)
+/* DSI V1 */
 #define DSI_PAD_CONTROL_VS1_PDIO(x)	(((x) & 0xf) <<  0)
 #define DSI_PAD_CONTROL_VS1_PDIO_CLK	(1 <<  8)
 #define DSI_PAD_CONTROL_VS1_PULLDN(x)	(((x) & 0xf) << 16)
@@ -140,4 +150,9 @@ enum tegra_dsi_format {
 	TEGRA_DSI_FORMAT_24P,
 };
 
+enum tegra_dsi_version {
+	TEGRA_DSI_V0,
+	TEGRA_DSI_V1,
+};
+
 #endif
-- 
2.48.1

Re: [PATCH v2 3/4 RESEND] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30

[Mikko Perttunen]

On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> Tegra20 and Tegra30 are fully compatible with existing tegra DSI driver
> apart from clock configuration and PAD calibration which are addressed by
> this patch.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/gpu/drm/tegra/drm.c |  2 +
>  drivers/gpu/drm/tegra/dsi.c | 88 ++++++++++++++++++++++++-------------
>  drivers/gpu/drm/tegra/dsi.h | 15 +++++++
>  3 files changed, 74 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
> index 4596073fe28f..5d64cd57e764 100644
> --- a/drivers/gpu/drm/tegra/drm.c
> +++ b/drivers/gpu/drm/tegra/drm.c
> @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
>  
>  static const struct of_device_id host1x_drm_subdevs[] = {
>  	{ .compatible = "nvidia,tegra20-dc", },
> +	{ .compatible = "nvidia,tegra20-dsi", },
>  	{ .compatible = "nvidia,tegra20-hdmi", },
>  	{ .compatible = "nvidia,tegra20-gr2d", },
>  	{ .compatible = "nvidia,tegra20-gr3d", },
>  	{ .compatible = "nvidia,tegra30-dc", },
> +	{ .compatible = "nvidia,tegra30-dsi", },
>  	{ .compatible = "nvidia,tegra30-hdmi", },
>  	{ .compatible = "nvidia,tegra30-gr2d", },
>  	{ .compatible = "nvidia,tegra30-gr3d", },
> diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> index 8e80c7efe8b4..d079aa7d2a85 100644
> --- a/drivers/gpu/drm/tegra/dsi.c
> +++ b/drivers/gpu/drm/tegra/dsi.c
> @@ -53,6 +53,10 @@ to_dsi_state(struct drm_connector_state *state)
>  	return container_of(state, struct tegra_dsi_state, base);
>  }
>  
> +struct tegra_dsi_config {
> +	u32 dsi_version;

Rather than a dsi_version field, we should have something that describes the difference. e.g. 'bool has_multiple_pad_controls' being true for the "V1" hardware.

> +};
> +
>  struct tegra_dsi {
>  	struct host1x_client client;
>  	struct tegra_output output;
> @@ -82,6 +86,8 @@ struct tegra_dsi {
>  	/* for ganged-mode support */
>  	struct tegra_dsi *master;
>  	struct tegra_dsi *slave;
> +
> +	const struct tegra_dsi_config *config;
>  };
>  
>  static inline struct tegra_dsi *
> @@ -663,39 +669,46 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
>  {
>  	u32 value;
>  
> -	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
> -	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> +	if (dsi->config->dsi_version == TEGRA_DSI_V1) {
> +		/*
> +		 * XXX Is this still needed? The module reset is deasserted right
> +		 * before this function is called.
> +		 */
> +		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
> +		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
> +		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
> +		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
> +		tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
> +
> +		value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
> +		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> +
> +		value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
> +			DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
> +			DSI_PAD_OUT_CLK(0x0);
> +		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
> +
> +		value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
> +			DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
> +		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
> +	} else {
> +		value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) |
> +			DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) |
> +			DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) |
> +			DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0);
> +		tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> +	}
>  
>  	return 0;
>  }
>  
>  static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
>  {
> -	u32 value;
>  	int err;
>  
> -	/*
> -	 * XXX Is this still needed? The module reset is deasserted right
> -	 * before this function is called.
> -	 */
> -	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
> -	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
> -	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
> -	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
> -	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
> -
>  	/* start calibration */
>  	tegra_dsi_pad_enable(dsi);
>  
> -	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
> -		DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
> -		DSI_PAD_OUT_CLK(0x0);
> -	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
> -
> -	value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
> -		DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
> -	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
> -
>  	err = tegra_mipi_start_calibration(dsi->mipi);
>  	if (err < 0)
>  		return err;
> @@ -1577,6 +1590,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
>  	if (!dsi)
>  		return -ENOMEM;
>  
> +	dsi->config = of_device_get_match_data(&pdev->dev);
>  	dsi->output.dev = dsi->dev = &pdev->dev;
>  	dsi->video_fifo_depth = 1920;
>  	dsi->host_fifo_depth = 64;
> @@ -1615,7 +1629,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
>  		goto remove;
>  	}
>  
> -	dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
> +	dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp");
>  	if (IS_ERR(dsi->clk_lp)) {
>  		err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
>  				    "cannot get low-power clock\n");
> @@ -1636,10 +1650,12 @@ static int tegra_dsi_probe(struct platform_device *pdev)
>  		goto remove;
>  	}
>  
> -	err = tegra_dsi_setup_clocks(dsi);

> -	if (err < 0) {
> -		dev_err(&pdev->dev, "cannot setup clocks\n");
> -		goto remove;
> +	if (dsi->config->dsi_version == TEGRA_DSI_V1) {

And 'has_mux_parent_clk', perhaps? Not a very good name, if you come up with something better feel free to use it.

I checked, and looks like Tegra30 in fact allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2, it is just not modelled in the clock driver. The same applies to all of Tegra114, 124, and 210, but only Tegra114 has it presently modelled as a mux whereas 124 and 210 have a gate. The TRMs for 124 and 210 specify that only PLL_D can be used in the mux bit documentation so the bit is probably dysfunctional on those chips.

The correct solution, hence, I think is to have that config field, and it be false for Tegra20, 124, and 210; and true for Tegra30, and 114. Then implement the mux clock in the Tegra30 clock driver.

However, I would settle for setting it to false for both Tegra20 and Tegra30 and leaving a comment next to the Tegra30 entry describing the situation (the mux clock is not currently modelled).

Cheers,
Mikko

> +		err = tegra_dsi_setup_clocks(dsi);
> +		if (err < 0) {
> +			dev_err(&pdev->dev, "cannot setup clocks\n");
> +			goto remove;
> +		}
>  	}
>  
>  	dsi->regs = devm_platform_ioremap_resource(pdev, 0);
> @@ -1703,11 +1719,21 @@ static void tegra_dsi_remove(struct platform_device *pdev)
>  	tegra_mipi_free(dsi->mipi);
>  }
>  
> +static const struct tegra_dsi_config tegra20_dsi_config = {
> +	.dsi_version = TEGRA_DSI_V0,
> +};
> +
> +static const struct tegra_dsi_config tegra114_dsi_config = {
> +	.dsi_version = TEGRA_DSI_V1,
> +};
> +
>  static const struct of_device_id tegra_dsi_of_match[] = {
> -	{ .compatible = "nvidia,tegra210-dsi", },
> -	{ .compatible = "nvidia,tegra132-dsi", },
> -	{ .compatible = "nvidia,tegra124-dsi", },
> -	{ .compatible = "nvidia,tegra114-dsi", },
> +	{ .compatible = "nvidia,tegra210-dsi", .data = &tegra114_dsi_config },
> +	{ .compatible = "nvidia,tegra132-dsi", .data = &tegra114_dsi_config },
> +	{ .compatible = "nvidia,tegra124-dsi", .data = &tegra114_dsi_config },
> +	{ .compatible = "nvidia,tegra114-dsi", .data = &tegra114_dsi_config },
> +	{ .compatible = "nvidia,tegra30-dsi", .data = &tegra20_dsi_config },
> +	{ .compatible = "nvidia,tegra20-dsi", .data = &tegra20_dsi_config },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
> diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h
> index f39594e65e97..5049ec7813c7 100644
> --- a/drivers/gpu/drm/tegra/dsi.h
> +++ b/drivers/gpu/drm/tegra/dsi.h
> @@ -95,6 +95,16 @@
>  #define DSI_TALLY_LRX(x)		(((x) & 0xff) <<  8)
>  #define DSI_TALLY_HTX(x)		(((x) & 0xff) <<  0)
>  #define DSI_PAD_CONTROL_0		0x4b
> +/* DSI V0 */
> +#define DSI_PAD_CONTROL_PULLDN_ENAB(x)	(((x) & 0x1) << 28)
> +#define DSI_PAD_CONTROL_SLEWUPADJ(x)	(((x) & 0x7) << 24)
> +#define DSI_PAD_CONTROL_SLEWDNADJ(x)	(((x) & 0x7) << 20)
> +#define DSI_PAD_CONTROL_PREEMP_EN(x)	(((x) & 0x1) << 19)
> +#define DSI_PAD_CONTROL_PDIO_CLK(x)	(((x) & 0x1) << 18)
> +#define DSI_PAD_CONTROL_PDIO(x)		(((x) & 0x3) << 16)
> +#define DSI_PAD_CONTROL_LPUPADJ(x)	(((x) & 0x3) << 14)
> +#define DSI_PAD_CONTROL_LPDNADJ(x)	(((x) & 0x3) << 12)
> +/* DSI V1 */
>  #define DSI_PAD_CONTROL_VS1_PDIO(x)	(((x) & 0xf) <<  0)
>  #define DSI_PAD_CONTROL_VS1_PDIO_CLK	(1 <<  8)
>  #define DSI_PAD_CONTROL_VS1_PULLDN(x)	(((x) & 0xf) << 16)
> @@ -140,4 +150,9 @@ enum tegra_dsi_format {
>  	TEGRA_DSI_FORMAT_24P,
>  };
>  
> +enum tegra_dsi_version {
> +	TEGRA_DSI_V0,
> +	TEGRA_DSI_V1,
> +};
> +
>  #endif
> 

Re: [PATCH v2 3/4 RESEND] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30

[Svyatoslav Ryhel]

чт, 15 січ. 2026 р. о 09:02 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> > Tegra20 and Tegra30 are fully compatible with existing tegra DSI driver
> > apart from clock configuration and PAD calibration which are addressed by
> > this patch.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  drivers/gpu/drm/tegra/drm.c |  2 +
> >  drivers/gpu/drm/tegra/dsi.c | 88 ++++++++++++++++++++++++-------------
> >  drivers/gpu/drm/tegra/dsi.h | 15 +++++++
> >  3 files changed, 74 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
> > index 4596073fe28f..5d64cd57e764 100644
> > --- a/drivers/gpu/drm/tegra/drm.c
> > +++ b/drivers/gpu/drm/tegra/drm.c
> > @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
> >
> >  static const struct of_device_id host1x_drm_subdevs[] = {
> >       { .compatible = "nvidia,tegra20-dc", },
> > +     { .compatible = "nvidia,tegra20-dsi", },
> >       { .compatible = "nvidia,tegra20-hdmi", },
> >       { .compatible = "nvidia,tegra20-gr2d", },
> >       { .compatible = "nvidia,tegra20-gr3d", },
> >       { .compatible = "nvidia,tegra30-dc", },
> > +     { .compatible = "nvidia,tegra30-dsi", },
> >       { .compatible = "nvidia,tegra30-hdmi", },
> >       { .compatible = "nvidia,tegra30-gr2d", },
> >       { .compatible = "nvidia,tegra30-gr3d", },
> > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> > index 8e80c7efe8b4..d079aa7d2a85 100644
> > --- a/drivers/gpu/drm/tegra/dsi.c
> > +++ b/drivers/gpu/drm/tegra/dsi.c
> > @@ -53,6 +53,10 @@ to_dsi_state(struct drm_connector_state *state)
> >       return container_of(state, struct tegra_dsi_state, base);
> >  }
> >
> > +struct tegra_dsi_config {
> > +     u32 dsi_version;
>
> Rather than a dsi_version field, we should have something that describes the difference. e.g. 'bool has_multiple_pad_controls' being true for the "V1" hardware.
>

I used versioning from downstream dsi sources, where with addition of
Tegra114 support older DSI controller got v0 and newer v1, but if you
find 'has_multiple_pad_controls' more suitable I have no objections.

> > +};
> > +
> >  struct tegra_dsi {
> >       struct host1x_client client;
> >       struct tegra_output output;
> > @@ -82,6 +86,8 @@ struct tegra_dsi {
> >       /* for ganged-mode support */
> >       struct tegra_dsi *master;
> >       struct tegra_dsi *slave;
> > +
> > +     const struct tegra_dsi_config *config;
> >  };
> >
> >  static inline struct tegra_dsi *
> > @@ -663,39 +669,46 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
> >  {
> >       u32 value;
> >
> > -     value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
> > -     tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> > +     if (dsi->config->dsi_version == TEGRA_DSI_V1) {
> > +             /*
> > +              * XXX Is this still needed? The module reset is deasserted right
> > +              * before this function is called.
> > +              */
> > +             tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
> > +             tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
> > +             tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
> > +             tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
> > +             tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
> > +
> > +             value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
> > +             tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> > +
> > +             value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
> > +                     DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
> > +                     DSI_PAD_OUT_CLK(0x0);
> > +             tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
> > +
> > +             value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
> > +                     DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
> > +             tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
> > +     } else {
> > +             value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) |
> > +                     DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) |
> > +                     DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) |
> > +                     DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0);
> > +             tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> > +     }
> >
> >       return 0;
> >  }
> >
> >  static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
> >  {
> > -     u32 value;
> >       int err;
> >
> > -     /*
> > -      * XXX Is this still needed? The module reset is deasserted right
> > -      * before this function is called.
> > -      */
> > -     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
> > -     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
> > -     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
> > -     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
> > -     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
> > -
> >       /* start calibration */
> >       tegra_dsi_pad_enable(dsi);
> >
> > -     value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
> > -             DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
> > -             DSI_PAD_OUT_CLK(0x0);
> > -     tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
> > -
> > -     value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
> > -             DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
> > -     tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
> > -
> >       err = tegra_mipi_start_calibration(dsi->mipi);
> >       if (err < 0)
> >               return err;
> > @@ -1577,6 +1590,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
> >       if (!dsi)
> >               return -ENOMEM;
> >
> > +     dsi->config = of_device_get_match_data(&pdev->dev);
> >       dsi->output.dev = dsi->dev = &pdev->dev;
> >       dsi->video_fifo_depth = 1920;
> >       dsi->host_fifo_depth = 64;
> > @@ -1615,7 +1629,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
> >               goto remove;
> >       }
> >
> > -     dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
> > +     dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp");
> >       if (IS_ERR(dsi->clk_lp)) {
> >               err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
> >                                   "cannot get low-power clock\n");
> > @@ -1636,10 +1650,12 @@ static int tegra_dsi_probe(struct platform_device *pdev)
> >               goto remove;
> >       }
> >
> > -     err = tegra_dsi_setup_clocks(dsi);
>
> > -     if (err < 0) {
> > -             dev_err(&pdev->dev, "cannot setup clocks\n");
> > -             goto remove;
> > +     if (dsi->config->dsi_version == TEGRA_DSI_V1) {
>
> And 'has_mux_parent_clk', perhaps? Not a very good name, if you come up with something better feel free to use it.

Noted

>
> I checked, and looks like Tegra30 in fact allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2, it is just not modelled in the clock driver. The same applies to all of Tegra114, 124, and 210, but only Tegra114 has it presently modelled as a mux whereas 124 and 210 have a gate. The TRMs for 124 and 210 specify that only PLL_D can be used in the mux bit documentation so the bit is probably dysfunctional on those chips.
>
> The correct solution, hence, I think is to have that config field, and it be false for Tegra20, 124, and 210; and true for Tegra30, and 114. Then implement the mux clock in the Tegra30 clock driver.
>
> However, I would settle for setting it to false for both Tegra20 and Tegra30 and leaving a comment next to the Tegra30 entry describing the situation (the mux clock is not currently modelled).
>

I clearly understand your point. I agree regarding setting it to false
for both Tegra20 and Tegra30 and leaving a comment for Tegra30, it
seems to be the optimal solution. Later on if there would be such
need, Tegra30 can get its mux too.

A little note regarding mux on Tegra124/210, it seems that bit is not
dysfunctional but behavior is intentional to diverge PLLD and D2 as
"internal" and "external" main display clock. At least this is what I
have concluded while working with Tegra display controller stuff.

> Cheers,
> Mikko
>

Thank you for your review!

Best regards,
Svyatoslav R.

> > +             err = tegra_dsi_setup_clocks(dsi);
> > +             if (err < 0) {
> > +                     dev_err(&pdev->dev, "cannot setup clocks\n");
> > +                     goto remove;
> > +             }
> >       }
> >
> >       dsi->regs = devm_platform_ioremap_resource(pdev, 0);
> > @@ -1703,11 +1719,21 @@ static void tegra_dsi_remove(struct platform_device *pdev)
> >       tegra_mipi_free(dsi->mipi);
> >  }
> >
> > +static const struct tegra_dsi_config tegra20_dsi_config = {
> > +     .dsi_version = TEGRA_DSI_V0,
> > +};
> > +
> > +static const struct tegra_dsi_config tegra114_dsi_config = {
> > +     .dsi_version = TEGRA_DSI_V1,
> > +};
> > +
> >  static const struct of_device_id tegra_dsi_of_match[] = {
> > -     { .compatible = "nvidia,tegra210-dsi", },
> > -     { .compatible = "nvidia,tegra132-dsi", },
> > -     { .compatible = "nvidia,tegra124-dsi", },
> > -     { .compatible = "nvidia,tegra114-dsi", },
> > +     { .compatible = "nvidia,tegra210-dsi", .data = &tegra114_dsi_config },
> > +     { .compatible = "nvidia,tegra132-dsi", .data = &tegra114_dsi_config },
> > +     { .compatible = "nvidia,tegra124-dsi", .data = &tegra114_dsi_config },
> > +     { .compatible = "nvidia,tegra114-dsi", .data = &tegra114_dsi_config },
> > +     { .compatible = "nvidia,tegra30-dsi", .data = &tegra20_dsi_config },
> > +     { .compatible = "nvidia,tegra20-dsi", .data = &tegra20_dsi_config },
> >       { },
> >  };
> >  MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
> > diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h
> > index f39594e65e97..5049ec7813c7 100644
> > --- a/drivers/gpu/drm/tegra/dsi.h
> > +++ b/drivers/gpu/drm/tegra/dsi.h
> > @@ -95,6 +95,16 @@
> >  #define DSI_TALLY_LRX(x)             (((x) & 0xff) <<  8)
> >  #define DSI_TALLY_HTX(x)             (((x) & 0xff) <<  0)
> >  #define DSI_PAD_CONTROL_0            0x4b
> > +/* DSI V0 */
> > +#define DSI_PAD_CONTROL_PULLDN_ENAB(x)       (((x) & 0x1) << 28)
> > +#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24)
> > +#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20)
> > +#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19)
> > +#define DSI_PAD_CONTROL_PDIO_CLK(x)  (((x) & 0x1) << 18)
> > +#define DSI_PAD_CONTROL_PDIO(x)              (((x) & 0x3) << 16)
> > +#define DSI_PAD_CONTROL_LPUPADJ(x)   (((x) & 0x3) << 14)
> > +#define DSI_PAD_CONTROL_LPDNADJ(x)   (((x) & 0x3) << 12)
> > +/* DSI V1 */
> >  #define DSI_PAD_CONTROL_VS1_PDIO(x)  (((x) & 0xf) <<  0)
> >  #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 <<  8)
> >  #define DSI_PAD_CONTROL_VS1_PULLDN(x)        (((x) & 0xf) << 16)
> > @@ -140,4 +150,9 @@ enum tegra_dsi_format {
> >       TEGRA_DSI_FORMAT_24P,
> >  };
> >
> > +enum tegra_dsi_version {
> > +     TEGRA_DSI_V0,
> > +     TEGRA_DSI_V1,
> > +};
> > +
> >  #endif
> >
>
>
>
>

[PATCH v2 4/4 RESEND] ARM: tegra: adjust DSI nodes for Tegra20/Tegra30

[Svyatoslav Ryhel]

Add missing nvidia,mipi-calibrate and cells properties to DSI nodes.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra20.dtsi | 4 ++++
 arch/arm/boot/dts/nvidia/tegra30.dtsi | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi
index 5cdbf1246cf8..39c0f791c7ee 100644
--- a/arch/arm/boot/dts/nvidia/tegra20.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi
@@ -238,7 +238,11 @@ dsi@54300000 {
 			reset-names = "dsi";
 			power-domains = <&pd_core>;
 			operating-points-v2 = <&dsi_dvfs_opp_table>;
+			nvidia,mipi-calibrate = <&csi 3>; /* DSI pad */
 			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi
index be752a245a55..fecd4891e751 100644
--- a/arch/arm/boot/dts/nvidia/tegra30.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi
@@ -343,7 +343,11 @@ dsi@54300000 {
 			reset-names = "dsi";
 			power-domains = <&pd_core>;
 			operating-points-v2 = <&dsia_dvfs_opp_table>;
+			nvidia,mipi-calibrate = <&csi 3>; /* DSIA pad */
 			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
 		};
 
 		dsi@54400000 {
@@ -356,7 +360,11 @@ dsi@54400000 {
 			reset-names = "dsi";
 			power-domains = <&pd_core>;
 			operating-points-v2 = <&dsib_dvfs_opp_table>;
+			nvidia,mipi-calibrate = <&csi 4>; /* DSIB pad */
 			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
 		};
 	};
 
-- 
2.48.1

Re: [PATCH v2 4/4 RESEND] ARM: tegra: adjust DSI nodes for Tegra20/Tegra30

[Mikko Perttunen]

On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> Add missing nvidia,mipi-calibrate and cells properties to DSI nodes.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra20.dtsi | 4 ++++
>  arch/arm/boot/dts/nvidia/tegra30.dtsi | 8 ++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi
> index 5cdbf1246cf8..39c0f791c7ee 100644
> --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi
> @@ -238,7 +238,11 @@ dsi@54300000 {
>  			reset-names = "dsi";
>  			power-domains = <&pd_core>;
>  			operating-points-v2 = <&dsi_dvfs_opp_table>;
> +			nvidia,mipi-calibrate = <&csi 3>; /* DSI pad */
>  			status = "disabled";
> +
> +			#address-cells = <1>;
> +			#size-cells = <0>;
>  		};
>  	};
>  
> diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi
> index be752a245a55..fecd4891e751 100644
> --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi
> @@ -343,7 +343,11 @@ dsi@54300000 {
>  			reset-names = "dsi";
>  			power-domains = <&pd_core>;
>  			operating-points-v2 = <&dsia_dvfs_opp_table>;
> +			nvidia,mipi-calibrate = <&csi 3>; /* DSIA pad */
>  			status = "disabled";
> +
> +			#address-cells = <1>;
> +			#size-cells = <0>;
>  		};
>  
>  		dsi@54400000 {
> @@ -356,7 +360,11 @@ dsi@54400000 {
>  			reset-names = "dsi";
>  			power-domains = <&pd_core>;
>  			operating-points-v2 = <&dsib_dvfs_opp_table>;
> +			nvidia,mipi-calibrate = <&csi 4>; /* DSIB pad */
>  			status = "disabled";
> +
> +			#address-cells = <1>;
> +			#size-cells = <0>;
>  		};
>  	};
>  
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v2 4/4 RESEND] ARM: tegra: adjust DSI nodes for Tegra20/Tegra30

[Thierry Reding]

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On Thu, Dec 04, 2025 at 08:17:03AM +0200, Svyatoslav Ryhel wrote:
> Add missing nvidia,mipi-calibrate and cells properties to DSI nodes.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra20.dtsi | 4 ++++
>  arch/arm/boot/dts/nvidia/tegra30.dtsi | 8 ++++++++
>  2 files changed, 12 insertions(+)

Applied, thanks.

Thierry

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Re: (subset) [PATCH v2 0/4 RESEND] gpu/drm: tegra: add DSI support for Tegra20/Tegra30

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>


On Thu, 04 Dec 2025 08:16:59 +0200, Svyatoslav Ryhel wrote:
> Tegra20/Tegra30 DSI is quite similar to Tegra114+ apart MIPI calibration
> logic and clocks. With a few minor tweaks, existing tegra DSI driver
> should work on Tegra20/Tegra30 devices just fine. Tested on
> Motorola Atrix 4G (T20) and ASUS VivoTab RT TF600T (T30).
> 
> This patchset depends on Tegra20/Tegra30 CSI bringup since both share
> MIPI calibration logic. Ideally these patches should be picked after
> CSI bringup but they will not break anything even if picked before
> CSI patches.
> 
> [...]

Applied, thanks!

[4/4] ARM: tegra: adjust DSI nodes for Tegra20/Tegra30
      (no commit info)

Best regards,
-- 
Thierry Reding <treding@nvidia.com>