Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of dw_pcie_wait_for_link() API

[Niklas Cassel <cassel@kernel.org>]

Hello Shawn,

On Wed, Jan 21, 2026 at 08:45:39PM +0800, Shawn Lin wrote:
> 在 2026/01/02 星期五 20:01, Niklas Cassel 写道:
> 
> Hi Niklas,
> 
> Sorry for chiming in on this so late. There is a register called
> PCIE_CLIENT_GENERAL_DEBUG_CON you may find on RK3588 TRM, you could
> hold LTSSM on EP side in DETECT_QUIET before enabling trainning, by
> setting BIT(6). And when EP side is ready to go, just clear BIT(6),
> so the link is able to be established and host side can rescan to
> find the EP properly.

Thank you for the suggestion.

Reading the register description of this debug control register.
For as log as sd_hold_ltssm is set, the controller stays in the
current LTSSM.

We could probably set this on the EP side, and only when starting
the link do we clear this bit.

However, I think that Mani's current proposal:
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dwc&id=01d16b8afb7afcc17f999f8b4a9b9cfe6c6fae71


Will work with more controllers running in EP mode, not just rk3588.

Also, when powering on both boards at the same time, it is possible that
the host side driver gets probed before the EP side.
If the EP side driver has not been probed to set bit sd_hold_ltssm,
the host will still see a load connected, but link training will fail,
so it will still jump to Poll.Compliance.

So AFAICT, Mani's proposal:
1) Seems more generic.
2) Seems less racy.


Kind regards,
Niklas