From: Niklas Cassel <cassel@kernel.org>
To: Aksh Garg <a-garg7@ti.com>
Cc: linux-pci@vger.kernel.org, jingoohan1@gmail.com, mani@kernel.org,
lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org,
bhelgaas@google.com, linux-kernel@vger.kernel.org,
s-vadapalli@ti.com, danishanwar@ti.com
Subject: Re: [PATCH v2 1/3] PCI: dwc: ep: Fix resizable BAR support for multi-PF configurations
Date: Thu, 22 Jan 2026 09:46:17 +0100 [thread overview]
Message-ID: <aXHjRBEE7H3WwGXH@ryzen> (raw)
In-Reply-To: <20260122082538.309122-2-a-garg7@ti.com>
On Thu, Jan 22, 2026 at 01:55:36PM +0530, Aksh Garg wrote:
> The resizable BAR support added by the commit 3a3d4cabe681
> ("PCI: dwc: ep: Allow EPF drivers to configure the size of Resizable
> BARs") incorrectly configures the resizable BARs only for the first
> Physical Function (PF0) in EP mode.
>
> The resizable BAR configuration functions use generic dw_pcie_*_dbi
> operations instead of physical function specific dw_pcie_ep_*_dbi
> operations. This causes resizable BAR configuration to always target
> PF0 regardless of the requested function number.
>
> Additionally, dw_pcie_ep_init_non_sticky_registers() only initializes
> resizable BAR registers for PF0, leaving other PFs unconfigured during
> the execution of this function.
>
> Fix this by using physical function specific configuration space access
> operations throughout the resizable BAR code path and initializing
> registers for all the physical functions that support resizable BARs.
>
> Fixes: 3a3d4cabe681 ("PCI: dwc: ep: Allow EPF drivers to configure the size of Resizable BARs")
> Signed-off-by: Aksh Garg <a-garg7@ti.com>
> Reviewed-by: Niklas Cassel <cassel@kernel.org>
> ---
>
> Link to v1:
> https://lore.kernel.org/all/20260121054214.274429-2-a-garg7@ti.com/
>
> Changes from v1 to v2:
> - Fixed the suggested nit
>
> .../pci/controller/dwc/pcie-designware-ep.c | 48 ++++++++++++-------
> 1 file changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 19571ac2b961..1458477a6ba9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -75,6 +75,13 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie_ep *ep, u8 func_no, u8 cap)
> cap, ep, func_no);
> }
>
> +static u16 dw_pcie_ep_find_ext_capability(struct dw_pcie_ep *ep,
> + u8 func_no, u8 cap)
> +{
> + return PCI_FIND_NEXT_EXT_CAP(dw_pcie_ep_read_cfg, 0,
> + cap, ep, func_no);
> +}
> +
> /**
> * dw_pcie_ep_hide_ext_capability - Hide a capability from the linked list
> * @pci: DWC PCI device
I'm not sure to which branch Mani wants to apply this series.
But if the answer is pci/controller/dwc then this patch will not apply,
because the context lines "dw_pcie_ep_hide_ext_capability()" specifically
has been removed there.
If he intends to put this patch on the endpoint branch, then this comment
can be disregarded.
Kind regards,
Niklas
next prev parent reply other threads:[~2026-01-22 8:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-22 8:25 [PATCH v2 0/3] PCI: dwc: ep: Enhance multi-function endpoint support Aksh Garg
2026-01-22 8:25 ` [PATCH v2 1/3] PCI: dwc: ep: Fix resizable BAR support for multi-PF configurations Aksh Garg
2026-01-22 8:46 ` Niklas Cassel [this message]
2026-01-22 8:25 ` [PATCH v2 2/3] PCI: dwc: ep: Add per-PF BAR and inbound ATU mapping support Aksh Garg
2026-01-22 8:25 ` [PATCH v2 3/3] PCI: dwc: ep: Add comment explaining controller-level PTM access Aksh Garg
2026-01-22 8:45 ` Niklas Cassel
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