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From: Daniel Golle <daniel@makrotopia.org>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Andrew Lunn <andrew@lunn.ch>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	Jonas Jelonek <jelonek.jonas@gmail.com>,
	Markus Stockhausen <markus.stockhausen@gmx.de>
Subject: Re: [RFC PATCH v2 2/2] net: mdio: rtl9300: setup PHY polling registers
Date: Thu, 22 Jan 2026 13:22:03 +0000	[thread overview]
Message-ID: <aXIke6nASlCSJVuF@makrotopia.org> (raw)
In-Reply-To: <aXITnCLt945xHqaP@shell.armlinux.org.uk>

On Thu, Jan 22, 2026 at 12:10:04PM +0000, Russell King (Oracle) wrote:
> On Thu, Jan 22, 2026 at 04:00:56AM +0000, Daniel Golle wrote:
> > +	/* Detect if PHY has 2.5G/5G/10G capabilities */
> > +	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported) ||
> > +	    linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, phydev->supported) ||
> > +	    linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, phydev->supported))
> > +		mac_type = SMI_MAC_TYPE_CTRL_2G_PLUS;
> > +	else
> > +		mac_type = SMI_MAC_TYPE_CTRL_1G;
> 
> There are PHYs which change their support depending on how they're
> configured, and there are PHYs that aren't configured correctly at
> probe time (and thus their ->supported mask is not correct.)

Oh, right...

> 
> The next thing I'm concerned about is the need to encode register
> information into this driver for each PHY that could be connected.
> Will there only be a small subset of PHYs that get used with this
> switch, or can any PHY be connected? If the latter, then encoding
> register information doesn't scale.

Only a small subset has been seen in the wild inside RealTek switches
for now. Most, of course, come with RealTek switches. However, it is
only very recently that RealTek offers 10G PHYs, so before vendors
were using 10G PHYs of other vendors, in practise I've only seen
Aquantia.

> 
> So, I don't think this is a good solution.
> 
> I'm wondering whether it would be better to have a callback through
> the bus when the PHY is connected with a netdev (in other words,
> after phy_init_hw() in phy_attach_direct()) which should be when
> the ->supported mask is fully up to date. This also means that the
> driver is bound, and we could then consider some kind of interface
> that would allow data about the PHY to be requested, such as register
> information. That would likely eliminate your need to test the
> phydev->supported bitmask (which I think is there to determine whether
> you need to tell your MDIO polling controller where certain registers
> are.)

Yes, that does sound better, especially with your concern about
->supported mask not necessarily being correct at probe time in mind.
It also makes more sense because it's only then that the interface
is in admin-up state and actually needs to be polled for a link.

Thank you for your thoughts and input on that. I'll discuss this
with the other OpenWrt folks involved with those switches and we'll
come up with a follow-up version.

  reply	other threads:[~2026-01-22 13:22 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-22  4:00 [RFC PATCH v2 0/2] net: mdio: setup RealTek MDIO polling registers Daniel Golle
2026-01-22  4:00 ` [RFC PATCH v2 1/2] net: phy: add (*register_phy)() hook to struct mii_bus Daniel Golle
2026-01-22  4:00 ` [RFC PATCH v2 2/2] net: mdio: rtl9300: setup PHY polling registers Daniel Golle
2026-01-22 12:10   ` Russell King (Oracle)
2026-01-22 13:22     ` Daniel Golle [this message]
2026-01-22 13:46       ` Andrew Lunn
2026-01-22 16:06         ` Daniel Golle

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