[PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids

[PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids

[Zhao Liu]

Hi,

This series advertises new instruction CPUIDs to userspace, which are
supported by Intel Diamond Rapids platform.

I've attached the spec link for each (family of) instruction in each
patch. Since the instructions included in this series don't require
additional enabling work, pass them through to guests directly.

This series is based on the master branch at the commit 23cb64fb7625
("Merge tag 'soc-fixes-6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc").

Thanks for your review!

Best Regards,
Zhao
---
Zhao Liu (4):
  KVM: x86: Advertise MOVRS CPUID to userspace
  KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace
  KVM: x86: Advertise AVX10.2 CPUID to userspace
  KVM: x86: Advertise AVX10_VNNI_INT CPUID to userspace

 arch/x86/include/asm/cpufeatures.h |  1 +
 arch/x86/include/asm/kvm_host.h    |  2 ++
 arch/x86/kvm/cpuid.c               | 46 ++++++++++++++++++++++++++++--
 arch/x86/kvm/reverse_cpuid.h       | 15 ++++++++++
 4 files changed, 62 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/4] KVM: x86: Advertise MOVRS CPUID to userspace

[Zhao Liu]

Define and pass MOVRS CPUID through to userspace.

MOVRS is a new set of instructions introduced in the Intel platform
Diamond Rapids, to provide load instructions that carry a read-shared
hint.

Functionally, MOVRS family is equivalent to existing load instructions,
but its read-shared hint indicates that the source memory location is
likely to become read-shared by multiple processors, i.e., read in the
future by at least one other processor before it is written (assuming it
is ever written in the future). This hint could optimize the behavior of
the caches, especially shared caches, for this data for future reads by
multiple processors. Additionally, MOVRS family also includes a software
prefetch instruction, PREFETCHRST2, that carries the same read-shared
hint. [*]

MOVRS family is enumerated by CPUID single-bit (0x7.0x1.EAX[bit 31]).
Since it's on a densely-populated CPUID leaf and some other bits on
this leaf have kernel usages, define this new feature in cpufeatures.h,
but hide it in /proc/cpuinfo due to lack of current kernel usage.

Advertise MOVRS bit to userspace directly. It's safe, since there's no
new VMX controls or additional host enabling required for guests to use
this feature.

[*]: Intel Architecture Instruction Set Extensions and Future Features
     (rev.059).

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/cpuid.c               | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 4091a776e37a..2d57bfe9c4c4 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -325,6 +325,7 @@
 #define X86_FEATURE_AMX_FP16		(12*32+21) /* AMX fp16 Support */
 #define X86_FEATURE_AVX_IFMA            (12*32+23) /* Support for VPMADD52[H,L]UQ */
 #define X86_FEATURE_LAM			(12*32+26) /* "lam" Linear Address Masking */
+#define X86_FEATURE_MOVRS		(12*32+31) /* MOVRS instructions */
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* "clzero" CLZERO instruction */
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 52524e0ca97f..372d82bae272 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1018,6 +1018,7 @@ void kvm_set_cpu_caps(void)
 		F(AMX_FP16),
 		F(AVX_IFMA),
 		F(LAM),
+		F(MOVRS),
 	);
 
 	kvm_cpu_cap_init(CPUID_7_1_ECX,
-- 
2.34.1

[PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Zhao Liu]

Define and pass AMX CPUIDs (0x1E.0x1) through to userspace.

Intel Diamond Rapids adds new AMX instructions to support new formats
and memory operations [*], and introduces the CPUID subleaf 0x1E.0x1
to centralize the discrete AMX feature bits within EAX.

Since these AMX features have no actual kernel usages, define them as
KVM-only features in reverse_cpuid.h.

In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are
mirrored positions of existing AMX feature bits distributed across the
0x7 leaves. To avoid duplicate feature names, name these mirror bits
with a *_MIRROR suffix, and define them in reverse_cpuid.h as KVM-only
features as well.

Advertise new CPUID subleaf 0x1E.0x1 with its AMX CPUID feature bits to
userspace for guest use. It's safe since no additional enabling work
is needed in the host kernel.

[*]: Intel Architecture Instruction Set Extensions and Future Features
     (rev.059).

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891
---
 arch/x86/include/asm/kvm_host.h |  1 +
 arch/x86/kvm/cpuid.c            | 25 +++++++++++++++++++++++++
 arch/x86/kvm/reverse_cpuid.h    | 11 +++++++++++
 3 files changed, 37 insertions(+)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 48598d017d6f..db7bf364f4fc 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -776,6 +776,7 @@ enum kvm_only_cpuid_leafs {
 	CPUID_24_0_EBX,
 	CPUID_8000_0021_ECX,
 	CPUID_7_1_ECX,
+	CPUID_1E_1_EAX,
 	NR_KVM_CPU_CAPS,
 
 	NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 372d82bae272..0795c9ecfd4b 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1057,6 +1057,17 @@ void kvm_set_cpu_caps(void)
 		SCATTERED_F(SGX_EDECCSSA),
 	);
 
+	kvm_cpu_cap_init(CPUID_1E_1_EAX,
+		F(AMX_INT8_MIRROR),
+		F(AMX_BF16_MIRROR),
+		F(AMX_COMPLEX_MIRROR),
+		F(AMX_FP16_MIRROR),
+		F(AMX_FP8),
+		F(AMX_TF32),
+		F(AMX_AVX512),
+		F(AMX_MOVRS),
+	);
+
 	kvm_cpu_cap_init(CPUID_24_0_EBX,
 		F(AVX10_128),
 		F(AVX10_256),
@@ -1616,6 +1627,20 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
 			break;
 		}
+
+		max_idx = entry->eax = min(entry->eax, 1u);
+
+		/* KVM only supports up to 0x1e.0x1, capped above via min(). */
+		if (max_idx >= 1) {
+			entry = do_host_cpuid(array, function, 1);
+			if (!entry)
+				goto out;
+
+			cpuid_entry_override(entry, CPUID_1E_1_EAX);
+			entry->ebx = 0;
+			entry->ecx = 0;
+			entry->edx = 0;
+		}
 		break;
 	case 0x24: {
 		u8 avx10_version;
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 743ab25ba787..99ec9e656655 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -44,6 +44,16 @@
 #define KVM_X86_FEATURE_BHI_CTRL	KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
 #define X86_FEATURE_MCDT_NO		KVM_X86_FEATURE(CPUID_7_2_EDX, 5)
 
+/* Intel-defined sub-features, CPUID level 0x0000001E:1 (EAX) */
+#define X86_FEATURE_AMX_INT8_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 0) /* Mirror of X86_FEATURE_AMX_INT8 */
+#define X86_FEATURE_AMX_BF16_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 1) /* Mirror of X86_FEATURE_AMX_BF16 */
+#define X86_FEATURE_AMX_COMPLEX_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 2) /* Mirror of X86_FEATURE_AMX_COMPLEX */
+#define X86_FEATURE_AMX_FP16_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 3) /* Mirror of X86_FEATURE_AMX_FP16 */
+#define X86_FEATURE_AMX_FP8		KVM_X86_FEATURE(CPUID_1E_1_EAX, 4)
+#define X86_FEATURE_AMX_TF32		KVM_X86_FEATURE(CPUID_1E_1_EAX, 6)
+#define X86_FEATURE_AMX_AVX512		KVM_X86_FEATURE(CPUID_1E_1_EAX, 7)
+#define X86_FEATURE_AMX_MOVRS		KVM_X86_FEATURE(CPUID_1E_1_EAX, 8)
+
 /* Intel-defined sub-features, CPUID level 0x00000024:0 (EBX) */
 #define X86_FEATURE_AVX10_128		KVM_X86_FEATURE(CPUID_24_0_EBX, 16)
 #define X86_FEATURE_AVX10_256		KVM_X86_FEATURE(CPUID_24_0_EBX, 17)
@@ -91,6 +101,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
 	[CPUID_24_0_EBX]      = {      0x24, 0, CPUID_EBX},
 	[CPUID_8000_0021_ECX] = {0x80000021, 0, CPUID_ECX},
 	[CPUID_7_1_ECX]       = {         7, 1, CPUID_ECX},
+	[CPUID_1E_1_EAX]      = {      0x1e, 1, CPUID_EAX},
 };
 
 /*
-- 
2.34.1

[PATCH 3/4] KVM: x86: Advertise AVX10.2 CPUID to userspace

[Zhao Liu]

Bump up the maximum supported AVX10 version and pass AVX10.2 through to
the guest.

Intel AVX10 Version 2 (Intel AVX10.2) includes a suite of new
instructions delivering new AI features and performance, accelerated
media processing, expanded Web Assembly, and Cryptography support, along
with enhancements to existing legacy instructions for completeness and
efficiency, and it is enumerated as version 2 in CPUID 0x24.0x0.EBX[bits
0-7] [1].

AVX10.2 has no current kernel usage and requires no additional host
kernel enabling work (based on AVX10.1 support) and provides no new
VMX controls [2]. Moreover, since AVX10.2 is the superset of AVX10.1,
there's no need to worry about AVX10.1 and AVX10.2 compatibility issues
in KVM.

Therefore, it's safe to advertise AVX10.2 version to userspace directly
if host supports AVX10.2.

[1]: Intel Advanced Vector Extensions 10.2 Architecture Specification
     (rev 5.0).
[2]: Note: Since AVX10.2 spec (rev 4.0), it has been declared "AVX10/512
     will be used in all Intel products, supporting vector lengths of
     128, 256, and 512 in all product lines", and the VMX support (in
     earlier revisions) for AVX10/256 guest on AVX10/512 host has been
     dropped.

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721
---
 arch/x86/kvm/cpuid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 0795c9ecfd4b..984fbee2795e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1655,7 +1655,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 		 * is guaranteed to be >=1 if AVX10 is supported.  Note #2, the
 		 * version needs to be captured before overriding EBX features!
 		 */
-		avx10_version = min_t(u8, entry->ebx & 0xff, 1);
+		avx10_version = min_t(u8, entry->ebx & 0xff, 2);
 		cpuid_entry_override(entry, CPUID_24_0_EBX);
 		entry->ebx |= avx10_version;
 
-- 
2.34.1

[PATCH 4/4] KVM: x86: Advertise AVX10_VNNI_INT CPUID to userspace

[Zhao Liu]

Define and pass AVX10_VNNI_INT CPUID through to the guest.

AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit
introduced on Intel Diamond Rapids, which enumerates the support for
EVEX VPDP* instructions for INT8/INT16 [*].

Since this feature has no actual kernel usages, define it as a KVM-only
feature in reverse_cpuid.h.

Advertise new CPUID subleaf 0x24.0x1 with AVX10_VNNI_INT bit to
userspace for guest use. It's safe since no additional enabling work
is needed in the host kernel.

[*]: Intel Advanced Vector Extensions 10.2 Architecture Specification
     (rev 5.0).

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721
---
 arch/x86/include/asm/kvm_host.h |  1 +
 arch/x86/kvm/cpuid.c            | 18 +++++++++++++++++-
 arch/x86/kvm/reverse_cpuid.h    |  4 ++++
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index db7bf364f4fc..992a0abbcc48 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -777,6 +777,7 @@ enum kvm_only_cpuid_leafs {
 	CPUID_8000_0021_ECX,
 	CPUID_7_1_ECX,
 	CPUID_1E_1_EAX,
+	CPUID_24_1_ECX,
 	NR_KVM_CPU_CAPS,
 
 	NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 984fbee2795e..58db5a87757e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1074,6 +1074,10 @@ void kvm_set_cpu_caps(void)
 		F(AVX10_512),
 	);
 
+	kvm_cpu_cap_init(CPUID_24_1_ECX,
+		F(AVX10_VNNI_INT),
+	);
+
 	kvm_cpu_cap_init(CPUID_8000_0001_ECX,
 		F(LAHF_LM),
 		F(CMP_LEGACY),
@@ -1650,6 +1654,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 			break;
 		}
 
+		max_idx = entry->eax = min(entry->eax, 1u);
 		/*
 		 * The AVX10 version is encoded in EBX[7:0].  Note, the version
 		 * is guaranteed to be >=1 if AVX10 is supported.  Note #2, the
@@ -1659,9 +1664,20 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 		cpuid_entry_override(entry, CPUID_24_0_EBX);
 		entry->ebx |= avx10_version;
 
-		entry->eax = 0;
 		entry->ecx = 0;
 		entry->edx = 0;
+
+		/* KVM only supports up to 0x24.0x1, capped above via min(). */
+		if (max_idx >= 1) {
+			entry = do_host_cpuid(array, function, 1);
+			if (!entry)
+				goto out;
+
+			cpuid_entry_override(entry, CPUID_24_1_ECX);
+			entry->eax = 0;
+			entry->ebx = 0;
+			entry->edx = 0;
+		}
 		break;
 	}
 	case KVM_CPUID_SIGNATURE: {
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index 99ec9e656655..a240abaaa5e0 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -59,6 +59,9 @@
 #define X86_FEATURE_AVX10_256		KVM_X86_FEATURE(CPUID_24_0_EBX, 17)
 #define X86_FEATURE_AVX10_512		KVM_X86_FEATURE(CPUID_24_0_EBX, 18)
 
+/* Intel-defined sub-features, CPUID level 0x00000024:1 (ECX) */
+#define X86_FEATURE_AVX10_VNNI_INT	KVM_X86_FEATURE(CPUID_24_1_ECX, 2)
+
 /* CPUID level 0x80000007 (EDX). */
 #define KVM_X86_FEATURE_CONSTANT_TSC	KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8)
 
@@ -102,6 +105,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
 	[CPUID_8000_0021_ECX] = {0x80000021, 0, CPUID_ECX},
 	[CPUID_7_1_ECX]       = {         7, 1, CPUID_ECX},
 	[CPUID_1E_1_EAX]      = {      0x1e, 1, CPUID_EAX},
+	[CPUID_24_1_ECX]      = {      0x24, 1, CPUID_ECX},
 };
 
 /*
-- 
2.34.1

Re: [PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids

[Paolo Bonzini]

> This series advertises new instruction CPUIDs to userspace, which are
> supported by Intel Diamond Rapids platform.
>
> I've attached the spec link for each (family of) instruction in each
> patch. Since the instructions included in this series don't require
> additional enabling work, pass them through to guests directly.
>
> This series is based on the master branch at the commit 23cb64fb7625
> ("Merge tag 'soc-fixes-6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc").

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>

I think these can wait for the next merge window since the corresponding
QEMU code will be released around the same time as 6.20.

Paolo

Re: [PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids

[Zhao Liu]

Hi Paolo and maintainers,

> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>

Thanks!

> I think these can wait for the next merge window since the corresponding
> QEMU code will be released around the same time as 6.20.

May I ask if this patch series can now be a candidate materials for v6.20?


Regards,
Zhao

Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Xiaoyao Li]

On 11/20/2025 1:07 PM, Zhao Liu wrote:
> In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are
> mirrored positions of existing AMX feature bits distributed across the
> 0x7 leaves. To avoid duplicate feature names, name these mirror bits
> with a *_MIRROR suffix, and define them in reverse_cpuid.h as KVM-only
> features as well.

It looks that KVM can emulate the mirroring CPUIDs regardless of whether 
hardware supports subleaf 1. However, given such emulation provides no 
real benefit but complicates KVM implementation, this patch looks good 
to me.

Re: [PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids

[Xiaoyao Li]

On 11/20/2025 1:07 PM, Zhao Liu wrote:
> Hi,
> 
> This series advertises new instruction CPUIDs to userspace, which are
> supported by Intel Diamond Rapids platform.
> 
> I've attached the spec link for each (family of) instruction in each
> patch. Since the instructions included in this series don't require
> additional enabling work, pass them through to guests directly.
> 
> This series is based on the master branch at the commit 23cb64fb7625
> ("Merge tag 'soc-fixes-6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc").
> 
> Thanks for your review!
> 
> Best Regards,
> Zhao
> ---
> Zhao Liu (4):
>    KVM: x86: Advertise MOVRS CPUID to userspace
>    KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace
>    KVM: x86: Advertise AVX10.2 CPUID to userspace
>    KVM: x86: Advertise AVX10_VNNI_INT CPUID to userspace

For the series,

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>

Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Sean Christopherson]

On Fri, Jan 23, 2026, Xiaoyao Li wrote:
> On 11/20/2025 1:07 PM, Zhao Liu wrote:
> > In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are
> > mirrored positions of existing AMX feature bits distributed across the
> > 0x7 leaves. To avoid duplicate feature names, name these mirror bits
> > with a *_MIRROR suffix, and define them in reverse_cpuid.h as KVM-only
> > features as well.
> 
> It looks that KVM can emulate the mirroring CPUIDs regardless of whether
> hardware supports subleaf 1. However, given such emulation provides no real
> benefit but complicates KVM implementation, this patch looks good to me.

Yeah, and it would run the risk of guest software doing stupid things like
assuming a certain CPU generation if the leaf is supported.

Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Sean Christopherson]

On Thu, Nov 20, 2025, Zhao Liu wrote:
> diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
> index 743ab25ba787..99ec9e656655 100644
> --- a/arch/x86/kvm/reverse_cpuid.h
> +++ b/arch/x86/kvm/reverse_cpuid.h
> @@ -44,6 +44,16 @@
>  #define KVM_X86_FEATURE_BHI_CTRL	KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
>  #define X86_FEATURE_MCDT_NO		KVM_X86_FEATURE(CPUID_7_2_EDX, 5)
>  
> +/* Intel-defined sub-features, CPUID level 0x0000001E:1 (EAX) */
> +#define X86_FEATURE_AMX_INT8_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 0) /* Mirror of X86_FEATURE_AMX_INT8 */
> +#define X86_FEATURE_AMX_BF16_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 1) /* Mirror of X86_FEATURE_AMX_BF16 */
> +#define X86_FEATURE_AMX_COMPLEX_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 2) /* Mirror of X86_FEATURE_AMX_COMPLEX */
> +#define X86_FEATURE_AMX_FP16_MIRROR	KVM_X86_FEATURE(CPUID_1E_1_EAX, 3) /* Mirror of X86_FEATURE_AMX_FP16 */

Unless someone feels *very* strongly about the "mirror" terminology, I'm going to
use ALIAS instead of MIRROR when applying, to match KVM's existing terminology for
the 8000_0001.EDX => 1.EDX aliases.

/*
 * Intel-defined sub-features, CPUID level 0x0000001E:1 (EAX).  Note, several
 * of the bits are aliases to features of the same name that are enumerated via
 * various CPUID.0x7 sub-leafs.
 */
#define X86_FEATURE_AMX_INT8_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 0)
#define X86_FEATURE_AMX_BF16_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 1)
#define X86_FEATURE_AMX_COMPLEX_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 2)
#define X86_FEATURE_AMX_FP16_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 3)

Re: [PATCH 1/4] KVM: x86: Advertise MOVRS CPUID to userspace

[Sean Christopherson]

On Thu, Nov 20, 2025, Zhao Liu wrote:
> Define and pass MOVRS CPUID through to userspace.

The feature isn't passed through, per KVM's terminology.  PASSTHROUGH_F() is
specifically for features where KVM deliberately ignores host kernel manipuation
and looks only at the raw CPUID output.

I'll tweak the wording when applying.

Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Sean Christopherson]

On Thu, Nov 20, 2025, Zhao Liu wrote:
> Define and pass AMX CPUIDs (0x1E.0x1) through to userspace.

Similar to the PASSTHROUGH_F() thing in the first patch, these aren't strictly
being passed through.  In practice, they are passed through as of the current
code base due to the features residing in KVM-only words, but I'd like to avoid
stating that features are being passed through unless KVM very deliberately wants
to ignore the kernel.

As before, I'll tweak when applying.  Same goes for patches 3 and 4.

Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Zhao Liu]

> Unless someone feels *very* strongly about the "mirror" terminology, I'm going to
> use ALIAS instead of MIRROR when applying, to match KVM's existing terminology for
> the 8000_0001.EDX => 1.EDX aliases.
> 
> /*
>  * Intel-defined sub-features, CPUID level 0x0000001E:1 (EAX).  Note, several
>  * of the bits are aliases to features of the same name that are enumerated via
>  * various CPUID.0x7 sub-leafs.
>  */
> #define X86_FEATURE_AMX_INT8_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 0)
> #define X86_FEATURE_AMX_BF16_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 1)
> #define X86_FEATURE_AMX_COMPLEX_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 2)
> #define X86_FEATURE_AMX_FP16_ALIAS	KVM_X86_FEATURE(CPUID_1E_1_EAX, 3)

LGTM, yes, ALIAS sounds better than MIRROR.

Thanks,
Zhao

Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace

[Zhao Liu]

On Fri, Jan 23, 2026 at 10:06:32AM -0800, Sean Christopherson wrote:
> Date: Fri, 23 Jan 2026 10:06:32 -0800
> From: Sean Christopherson <seanjc@google.com>
> Subject: Re: [PATCH 2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1
>  to userspace
> 
> On Thu, Nov 20, 2025, Zhao Liu wrote:
> > Define and pass AMX CPUIDs (0x1E.0x1) through to userspace.
> 
> Similar to the PASSTHROUGH_F() thing in the first patch, these aren't strictly
> being passed through.  In practice, they are passed through as of the current
> code base due to the features residing in KVM-only words, but I'd like to avoid
> stating that features are being passed through unless KVM very deliberately wants
> to ignore the kernel.

Good point, thanks for your reminder!

> As before, I'll tweak when applying.  Same goes for patches 3 and 4.

Thanks!

-Zhao

Re: [PATCH 0/4] KVM: x86: Advertise new instruction CPUIDs for Intel Diamond Rapids

[Sean Christopherson]

On Thu, 20 Nov 2025 13:07:16 +0800, Zhao Liu wrote:
> This series advertises new instruction CPUIDs to userspace, which are
> supported by Intel Diamond Rapids platform.
> 
> I've attached the spec link for each (family of) instruction in each
> patch. Since the instructions included in this series don't require
> additional enabling work, pass them through to guests directly.
> 
> [...]

Applied to kvm-x86 misc, thanks!

[1/4] KVM: x86: Advertise MOVRS CPUID to userspace
      https://github.com/kvm-x86/linux/commit/f24ef0093dd8
[2/4] KVM: x86: Advertise AMX CPUIDs in subleaf 0x1E.0x1 to userspace
      https://github.com/kvm-x86/linux/commit/58cbaf64e653
[3/4] KVM: x86: Advertise AVX10.2 CPUID to userspace
      https://github.com/kvm-x86/linux/commit/2ff8fb1e65e1
[4/4] KVM: x86: Advertise AVX10_VNNI_INT CPUID to userspace
      https://github.com/kvm-x86/linux/commit/062768f42689

--
https://github.com/kvm-x86/linux/tree/next