Re: [PATCH v6 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO

Re: [PATCH v6 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO

[Gary Lau]

Hi Stafford,

I should clarify my setup: I'm using hardware address translation to make the
OpenCores 8-bit GPIO appear as 32-bit to the CPU. Specifically:

1. Address translation: The CPU's 32-bit addresses are right-shifted by 2 bits
   (adr_i[2] in Verilog), so each 32-bit CPU access maps to the correct 8-bit
   OpenCores register.

2. Data width adaptation: Only dat_i[7:0] and dat_o[7:0] are connected, so
   32-bit writes are truncated to 8-bit, and reads are zero-extended.

This hardware wrapper makes brcm,bcm6345-gpio driver "work" with my OpenCores
GPIO, but it's really a hardware-level compatibility layer, not true software
compatibility.

So you're absolutely right that the native opencores,gpio isn't compatible
with brcm,bcm6345-gpio. My setup works because of custom hardware translation,
not because the IP cores are compatible.

Best regards,
Gary

Re: [PATCH v6 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO

[Stafford Horne]

On Fri, Jan 23, 2026 at 10:18:04PM +0800, Gary Lau wrote:
> Hi Stafford,
> 
> I should clarify my setup: I'm using hardware address translation to make the
> OpenCores 8-bit GPIO appear as 32-bit to the CPU. Specifically:
> 
> 1. Address translation: The CPU's 32-bit addresses are right-shifted by 2 bits
>    (adr_i[2] in Verilog), so each 32-bit CPU access maps to the correct 8-bit
>    OpenCores register.
> 
> 2. Data width adaptation: Only dat_i[7:0] and dat_o[7:0] are connected, so
>    32-bit writes are truncated to 8-bit, and reads are zero-extended.
> 
> This hardware wrapper makes brcm,bcm6345-gpio driver "work" with my OpenCores
> GPIO, but it's really a hardware-level compatibility layer, not true software
> compatibility.
> 
> So you're absolutely right that the native opencores,gpio isn't compatible
> with brcm,bcm6345-gpio. My setup works because of custom hardware translation,
> not because the IP cores are compatible.

Thanks Gary for testing.

-Stafford

Re: [PATCH v6 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO

[Gary Lau]

Hi Stafford,
I've tested the "brcm,bcm6345-gpio" driver with the OpenCores 8-bit GPIO core, and it is working as expected.
For reference, here is the hardware connection logic I used for the OpenRISC to OpenCores GPIO interface:
Verilog:
simple_gpio gpio0 (
    .clk_i  (clk_i),
    .rst_i  (rst_i),
    .cyc_i  (cyc_i & (|sel_i)),
    .stb_i  (stb_i & (|sel_i)),
    .adr_i  (adr_i[2]),
    .we_i   (we_i),
    .dat_i  (dat_i[7:0]),
    .ack_o  (ack_o),
    .dat_o  (dat_o[7:0]),
    .gpio   (gpio[7:0]),
    .gpio_i (gpio_i)
);
And here is the corresponding part of my dts:
gpio0: gpio@91000000 {
    compatible = "brcm,bcm6345-gpio";
    reg = <0x91000000 0x4>, <0x91000004 0x4>;
    reg-names = "dat", "dirout";
    gpio-controller;
    big-endian; 
    status = "okay";

[PATCH v6 0/6] OpenRISC de0 nano single and multicore boards

[Stafford Horne]

Since v5:
 - Adjust dt-binding patch based on suggestions from Geert and Krzysztof.
 - Add reviewed-by's on the dt-binding patch.
Since v4:
 - Rebased the series on linux-next to allow patches to be incremental.
 - Rewrote the dt-bindings patch as an incremental patch, Due to this I
   dropped reviewed-by's.
 - Added acked-by to the IPI fix patch.
Since v3:
 - Switch order of gpio-mmio driver and bindings patches to patch binding
   first before driver.  Suggested by Krzysztof.
 - Removed example form binding suggested by Krzysztof.
 - Added Reviewed-by's from Geert and Linus W.
Since v2:
 - Fixup (replace) gpio-mmio patch to update driver compatible list and just add
   opencores,gpio to mmio-gpio bindings.  Discussed with Geert and Linus W
   because the 8-bit opencores,gpio is not the same as the 32-bit broadcom
   chip. [1].
 - Update new device trees to use proper ordering, remove debug options, remove
   unneeded "status" properties.  Suggested by Geert.
Since v1:
 - Use proper schema in gpio-mmio suggsted by Conor Dooley
 - Remove 0 clock-frequency definitions in dtsi file

The patches add support for OpenRISC systems running on the De0 Nano FPGA
development board.  We have two SoCs which are available here:

 - https://github.com/olofk/de0_nano - Single core
 - https://github.com/stffrdhrn/de0_nano-multicore - Multicore

As I work on tutorials [2] to help other get started with OpenRISC I would like to
have these defconfig and devicetree definitions in the upstream kernel to avoid
losing them.

When I was working on resurrecting these old setup's I found a major bug in
OpenRISC SMP which is fixed in this series as well.

[1] https://lore.kernel.org/lkml/20251217080843.70621-1-shorne@gmail.com/
[2] https://openrisc.io/tutorials/

Stafford Horne (6):
  dt-bindings: gpio-mmio: Correct opencores GPIO
  gpio: mmio: Add compatible for opencores GPIO
  openrisc: dts: Add de0 nano config and devicetree
  openrisc: Fix IPIs on simple multicore systems
  openrisc: dts: Split simple smp dts to dts and dtsi
  openrisc: dts: Add de0 nano multicore config and devicetree

 .../devicetree/bindings/gpio/gpio-mmio.yaml   | 16 ++--
 arch/openrisc/boot/dts/de0-nano-common.dtsi   | 42 +++++++++
 arch/openrisc/boot/dts/de0-nano-multicore.dts | 25 +++++
 arch/openrisc/boot/dts/de0-nano.dts           | 54 +++++++++++
 arch/openrisc/boot/dts/simple-smp.dts         | 25 +++++
 .../dts/{simple_smp.dts => simple-smp.dtsi}   | 11 +--
 arch/openrisc/configs/de0_nano_defconfig      | 79 ++++++++++++++++
 .../configs/de0_nano_multicore_defconfig      | 92 +++++++++++++++++++
 arch/openrisc/configs/simple_smp_defconfig    |  2 +-
 arch/openrisc/include/asm/smp.h               |  3 +-
 arch/openrisc/kernel/smp.c                    | 22 ++++-
 drivers/gpio/gpio-mmio.c                      |  1 +
 drivers/irqchip/irq-ompic.c                   | 15 ++-
 drivers/irqchip/irq-or1k-pic.c                | 27 +++++-
 14 files changed, 390 insertions(+), 24 deletions(-)
 create mode 100644 arch/openrisc/boot/dts/de0-nano-common.dtsi
 create mode 100644 arch/openrisc/boot/dts/de0-nano-multicore.dts
 create mode 100644 arch/openrisc/boot/dts/de0-nano.dts
 create mode 100644 arch/openrisc/boot/dts/simple-smp.dts
 rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (90%)
 create mode 100644 arch/openrisc/configs/de0_nano_defconfig
 create mode 100644 arch/openrisc/configs/de0_nano_multicore_defconfig

-- 
2.51.0

[PATCH v6 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO

[Stafford Horne]

In commit f48b5e8bc2e1 ("dt-bindings: gpio-mmio: Add compatible string
for opencores,gpio") we marked opencores,gpio to be allowed with
brcm,bcm6345-gpio. This was wrong, opencores,gpio is not compatible with
brcm,bcm6345-gpio. It has a different register map and is 8-bit vs
Broadcom which is 32-bit. Change opencores,gpio to be a separate
compatible string for MMIO GPIO.

Also, as this change rewrote the entire enum, I took this opportunity to
alphabetically sort the list.

Fixes: f48b5e8bc2e1 ("dt-bindings: gpio-mmio: Add compatible string for opencores,gpio")
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Since v5:
 - Updated comment based on comments from Krzysztof and Geert.
 - Added reviewed-by's.
 - Sorted the enum list and added not to commit message based on comment
   from Krzysztof.
Since v4:
 - New patch.
 - Rebased old patch and rewrote commit message.

 .../devicetree/bindings/gpio/gpio-mmio.yaml      | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
index 7ee40b9bc562..1b2d253b19c1 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
@@ -18,16 +18,12 @@ description:
 
 properties:
   compatible:
-    oneOf:
-      - enum:
-          - brcm,bcm6345-gpio
-          - ni,169445-nand-gpio
-          - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
-          - intel,ixp4xx-expansion-bus-mmio-gpio
-      - items:
-          - enum:
-              - opencores,gpio
-          - const: brcm,bcm6345-gpio
+    enum:
+      - brcm,bcm6345-gpio
+      - intel,ixp4xx-expansion-bus-mmio-gpio
+      - ni,169445-nand-gpio
+      - opencores,gpio
+      - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
 
   big-endian: true
 
-- 
2.51.0

Re: [PATCH v6 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO

[Linus Walleij]

On Thu, Jan 15, 2026 at 4:10 PM Stafford Horne <shorne@gmail.com> wrote:

> In commit f48b5e8bc2e1 ("dt-bindings: gpio-mmio: Add compatible string
> for opencores,gpio") we marked opencores,gpio to be allowed with
> brcm,bcm6345-gpio. This was wrong, opencores,gpio is not compatible with
> brcm,bcm6345-gpio. It has a different register map and is 8-bit vs
> Broadcom which is 32-bit. Change opencores,gpio to be a separate
> compatible string for MMIO GPIO.
>
> Also, as this change rewrote the entire enum, I took this opportunity to
> alphabetically sort the list.
>
> Fixes: f48b5e8bc2e1 ("dt-bindings: gpio-mmio: Add compatible string for opencores,gpio")
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij