* [PATCH] clk: imx8mq: Correct the CSI PHY sels
@ 2026-01-27 23:47 Sebastian Krzyszkowiak
2026-01-28 3:39 ` Peng Fan
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Sebastian Krzyszkowiak @ 2026-01-27 23:47 UTC (permalink / raw)
To: Abel Vesa, Peng Fan, Michael Turquette, Stephen Boyd, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Lucas Stach,
Anson Huang
Cc: Bai Ping, linux-clk, imx, linux-arm-kernel, linux-kernel, kernel,
Sebastian Krzyszkowiak
According to i.MX 8M Quad Reference Manual (Section 5.1.2 Table 5-1)
MIPI_CSI1_PHY_REF_CLK_ROOT and MIPI_CSI2_PHY_REF_CLK_ROOT have
SYSTEM_PLL2_DIV3 available as their second source, which corresponds
to sys2_pll_333m rather than sys2_pll_125m.
Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
---
drivers/clk/imx/clk-imx8mq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index f70ed231b92d..cedc8a02aa1f 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -237,7 +237,7 @@ static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "
static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
-static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
@@ -246,7 +246,7 @@ static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m",
static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
-static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
+static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
---
base-commit: 63804fed149a6750ffd28610c5c1c98cce6bd377
change-id: 20260128-imx8mq-csi-clk-2da0c4741ed6
Best regards,
--
Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
^ permalink raw reply related [flat|nested] 5+ messages in thread* RE: [PATCH] clk: imx8mq: Correct the CSI PHY sels
2026-01-27 23:47 [PATCH] clk: imx8mq: Correct the CSI PHY sels Sebastian Krzyszkowiak
@ 2026-01-28 3:39 ` Peng Fan
2026-01-28 4:50 ` Jacky Bai
2026-01-28 5:56 ` Peng Fan
2026-03-18 15:39 ` Abel Vesa
2 siblings, 1 reply; 5+ messages in thread
From: Peng Fan @ 2026-01-28 3:39 UTC (permalink / raw)
To: Sebastian Krzyszkowiak, Abel Vesa, Michael Turquette,
Stephen Boyd, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Lucas Stach, Anson Huang
Cc: Jacky Bai, linux-clk@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@puri.sm
Hi Sebastian,
Thanks for your patch!
> Subject: [PATCH] clk: imx8mq: Correct the CSI PHY sels
>
> According to i.MX 8M Quad Reference Manual (Section 5.1.2 Table 5-1)
> MIPI_CSI1_PHY_REF_CLK_ROOT and MIPI_CSI2_PHY_REF_CLK_ROOT
> have
> SYSTEM_PLL2_DIV3 available as their second source, which
> corresponds to sys2_pll_333m rather than sys2_pll_125m.
After check the RM, you are right. But our internal doc shows
it is sys2_pll_125m, so I need to check the RTL code, then
back you later regarding this patch.
Thanks,
Peng.
>
> Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
> Signed-off-by: Sebastian Krzyszkowiak
> <sebastian.krzyszkowiak@puri.sm>
> ---
> drivers/clk/imx/clk-imx8mq.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-
> imx8mq.c index f70ed231b92d..cedc8a02aa1f 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -237,7 +237,7 @@ static const char * const imx8mq_dsi_esc_sels[]
> = {"osc_25m", "sys2_pll_100m", "
> static const char * const imx8mq_csi1_core_sels[] = {"osc_25m",
> "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
> "sys2_pll_1000m", "sys3_pll_out",
> "audio_pll2_out", "video_pll1_out", };
>
> -static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m",
> "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
> +static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m",
> +"sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
> "sys2_pll_1000m", "clk_ext2",
> "audio_pll2_out", "video_pll1_out", };
>
> static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m",
> "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", @@ -246,7
> +246,7 @@ static const char * const imx8mq_csi1_esc_sels[] =
> {"osc_25m", "sys2_pll_100m", static const char * const
> imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m",
> "sys2_pll_250m", "sys1_pll_800m",
> "sys2_pll_1000m", "sys3_pll_out",
> "audio_pll2_out", "video_pll1_out", };
>
> -static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m",
> "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
> +static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m",
> +"sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
> "sys2_pll_1000m", "clk_ext2",
> "audio_pll2_out", "video_pll1_out", };
>
> static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m",
> "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
>
> ---
> base-commit: 63804fed149a6750ffd28610c5c1c98cce6bd377
> change-id: 20260128-imx8mq-csi-clk-2da0c4741ed6
>
> Best regards,
> --
> Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
^ permalink raw reply [flat|nested] 5+ messages in thread* RE: [PATCH] clk: imx8mq: Correct the CSI PHY sels
2026-01-28 3:39 ` Peng Fan
@ 2026-01-28 4:50 ` Jacky Bai
0 siblings, 0 replies; 5+ messages in thread
From: Jacky Bai @ 2026-01-28 4:50 UTC (permalink / raw)
To: Peng Fan, Sebastian Krzyszkowiak, Abel Vesa, Michael Turquette,
Stephen Boyd, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Lucas Stach, Anson Huang
Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@puri.sm
> Subject: RE: [PATCH] clk: imx8mq: Correct the CSI PHY sels
>
> Hi Sebastian,
>
> Thanks for your patch!
>
> > Subject: [PATCH] clk: imx8mq: Correct the CSI PHY sels
> >
> > According to i.MX 8M Quad Reference Manual (Section 5.1.2 Table 5-1)
> > MIPI_CSI1_PHY_REF_CLK_ROOT and MIPI_CSI2_PHY_REF_CLK_ROOT have
> > SYSTEM_PLL2_DIV3 available as their second source, which corresponds
> > to sys2_pll_333m rather than sys2_pll_125m.
>
> After check the RM, you are right. But our internal doc shows it is
> sys2_pll_125m, so I need to check the RTL code, then back you later regarding
> this patch.
>
The changes are correct, the mux select '1' should be sys2_pll_333m.
BR
> Thanks,
> Peng.
>
> >
> > Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
> > Signed-off-by: Sebastian Krzyszkowiak
> > <sebastian.krzyszkowiak@puri.sm>
> > ---
> > drivers/clk/imx/clk-imx8mq.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-
> > imx8mq.c index f70ed231b92d..cedc8a02aa1f 100644
> > --- a/drivers/clk/imx/clk-imx8mq.c
> > +++ b/drivers/clk/imx/clk-imx8mq.c
> > @@ -237,7 +237,7 @@ static const char * const imx8mq_dsi_esc_sels[] =
> > {"osc_25m", "sys2_pll_100m", "
> > static const char * const imx8mq_csi1_core_sels[] = {"osc_25m",
> > "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
> > "sys2_pll_1000m",
> > "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
> >
> > -static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m",
> > "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
> > +static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m",
> > +"sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
> > "sys2_pll_1000m",
> > "clk_ext2", "audio_pll2_out", "video_pll1_out", };
> >
> > static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m",
> > "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", @@ -246,7
> > +246,7 @@ static const char * const imx8mq_csi1_esc_sels[] =
> > {"osc_25m", "sys2_pll_100m", static const char * const
> > imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m",
> > "sys2_pll_250m", "sys1_pll_800m",
> > "sys2_pll_1000m",
> > "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
> >
> > -static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m",
> > "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
> > +static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m",
> > +"sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
> > "sys2_pll_1000m",
> > "clk_ext2", "audio_pll2_out", "video_pll1_out", };
> >
> > static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m",
> > "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
> >
> > ---
> > base-commit: 63804fed149a6750ffd28610c5c1c98cce6bd377
> > change-id: 20260128-imx8mq-csi-clk-2da0c4741ed6
> >
> > Best regards,
> > --
> > Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: imx8mq: Correct the CSI PHY sels
2026-01-27 23:47 [PATCH] clk: imx8mq: Correct the CSI PHY sels Sebastian Krzyszkowiak
2026-01-28 3:39 ` Peng Fan
@ 2026-01-28 5:56 ` Peng Fan
2026-03-18 15:39 ` Abel Vesa
2 siblings, 0 replies; 5+ messages in thread
From: Peng Fan @ 2026-01-28 5:56 UTC (permalink / raw)
To: Sebastian Krzyszkowiak
Cc: Abel Vesa, Peng Fan, Michael Turquette, Stephen Boyd, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Lucas Stach,
Anson Huang, Bai Ping, linux-clk, imx, linux-arm-kernel,
linux-kernel, kernel
On Wed, Jan 28, 2026 at 12:47:21AM +0100, Sebastian Krzyszkowiak wrote:
>According to i.MX 8M Quad Reference Manual (Section 5.1.2 Table 5-1)
>MIPI_CSI1_PHY_REF_CLK_ROOT and MIPI_CSI2_PHY_REF_CLK_ROOT have
>SYSTEM_PLL2_DIV3 available as their second source, which corresponds
>to sys2_pll_333m rather than sys2_pll_125m.
>
>Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
>Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
Thanks for the fix.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] clk: imx8mq: Correct the CSI PHY sels
2026-01-27 23:47 [PATCH] clk: imx8mq: Correct the CSI PHY sels Sebastian Krzyszkowiak
2026-01-28 3:39 ` Peng Fan
2026-01-28 5:56 ` Peng Fan
@ 2026-03-18 15:39 ` Abel Vesa
2 siblings, 0 replies; 5+ messages in thread
From: Abel Vesa @ 2026-03-18 15:39 UTC (permalink / raw)
To: Abel Vesa, Peng Fan, Michael Turquette, Stephen Boyd, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Lucas Stach,
Anson Huang, Sebastian Krzyszkowiak
Cc: Bai Ping, linux-clk, imx, linux-arm-kernel, linux-kernel, kernel
On Wed, 28 Jan 2026 00:47:21 +0100, Sebastian Krzyszkowiak wrote:
> According to i.MX 8M Quad Reference Manual (Section 5.1.2 Table 5-1)
> MIPI_CSI1_PHY_REF_CLK_ROOT and MIPI_CSI2_PHY_REF_CLK_ROOT have
> SYSTEM_PLL2_DIV3 available as their second source, which corresponds
> to sys2_pll_333m rather than sys2_pll_125m.
Applied, thanks!
[1/1] clk: imx8mq: Correct the CSI PHY sels
commit: 4219a54681d183a143009104967645cc252f1e30
Best regards,
--
Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2026-01-27 23:47 [PATCH] clk: imx8mq: Correct the CSI PHY sels Sebastian Krzyszkowiak
2026-01-28 3:39 ` Peng Fan
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2026-01-28 5:56 ` Peng Fan
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