[PATCH v2 1/3] arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD

[PATCH v2 1/3] arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

During system resume, the following errors occurred:

  [  430.638625] mmc1: error -84 writing Cache Enable bit
  [  430.643618] mmc1: error -84 doing runtime resume

For eMMC and SD, there are two tuning pass windows and the gap between
those two windows may only have one cell. If tuning step > 1, the gap may
just be skipped and host assumes those two windows as a continuous
windows. This will cause a wrong delay cell near the gap to be selected.

Set the tuning step to 1 to avoid selecting the wrong delay cell.

For SDIO, the gap is sufficiently large, so the default tuning step does
not cause this issue.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
index 0852067eab2c..197c8f8b7f66 100644
--- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
@@ -507,6 +507,7 @@ &usdhc1 {
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	bus-width = <8>;
 	non-removable;
+	fsl,tuning-step = <1>;
 	status = "okay";
 };
 
@@ -519,6 +520,7 @@ &usdhc2 {
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	bus-width = <4>;
 	no-mmc;
+	fsl,tuning-step = <1>;
 	status = "okay";
 };
 
-- 
2.34.1

[PATCH v2 2/3] arm64: dts: imx93-11x11-evk: change usdhc tuning step for eMMC and SD

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

During system resume, the following errors occurred:

  [  430.638625] mmc1: error -84 writing Cache Enable bit
  [  430.643618] mmc1: error -84 doing runtime resume

For eMMC and SD, there are two tuning pass windows and the gap between
those two windows may only have one cell. If tuning step > 1, the gap may
just be skipped and host assumes those two windows as a continuous
windows. This will cause a wrong delay cell near the gap to be selected.

Set the tuning step to 1 to avoid selecting the wrong delay cell.

For SDIO, the gap is sufficiently large, so the default tuning step does
not cause this issue.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index b94a24193e19..6da2d25acbd0 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -632,6 +632,7 @@ &usdhc1 {
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	bus-width = <8>;
 	non-removable;
+	fsl,tuning-step = <1>;
 	status = "okay";
 };
 
@@ -644,6 +645,7 @@ &usdhc2 {
 	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	bus-width = <4>;
+	fsl,tuning-step = <1>;
 	status = "okay";
 	no-mmc;
 };
-- 
2.34.1

[PATCH v2 3/3] arm64: dts: imx91-11x11-evk: change usdhc tuning step for eMMC and SD

[ziniu.wang_1]

From: Luke Wang <ziniu.wang_1@nxp.com>

During system resume, the following errors occurred:

  [  430.638625] mmc1: error -84 writing Cache Enable bit
  [  430.643618] mmc1: error -84 doing runtime resume

For eMMC and SD, there are two tuning pass windows and the gap between
those two windows may only have one cell. If tuning step > 1, the gap may
just be skipped and host assumes those two windows as a continuous
windows. This will cause a wrong delay cell near the gap to be selected.

Set the tuning step to 1 to avoid selecting the wrong delay cell.

For SDIO, the gap is sufficiently large, so the default tuning step does
not cause this issue.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
index aca78768dbd4..4164d9e4e0fd 100644
--- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
@@ -415,6 +415,7 @@ &usdhc1 {
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	fsl,tuning-step = <1>;
 	status = "okay";
 };
 
@@ -429,6 +430,7 @@ &usdhc2 {
 	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 	vmmc-supply = <&reg_usdhc2_vmmc>;
+	fsl,tuning-step = <1>;
 	status = "okay";
 };
 
-- 
2.34.1

Re: [PATCH v2 1/3] arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD

[Frank Li]

On Thu, Jan 29, 2026 at 04:04:37PM +0800, ziniu.wang_1@nxp.com wrote:
> From: Luke Wang <ziniu.wang_1@nxp.com>
>
> During system resume, the following errors occurred:
>
>   [  430.638625] mmc1: error -84 writing Cache Enable bit
>   [  430.643618] mmc1: error -84 doing runtime resume
>
> For eMMC and SD, there are two tuning pass windows and the gap between
> those two windows may only have one cell. If tuning step > 1, the gap may
> just be skipped and host assumes those two windows as a continuous
> windows. This will cause a wrong delay cell near the gap to be selected.
>
> Set the tuning step to 1 to avoid selecting the wrong delay cell.
>
> For SDIO, the gap is sufficiently large, so the default tuning step does
> not cause this issue.
>
> Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> index 0852067eab2c..197c8f8b7f66 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> @@ -507,6 +507,7 @@ &usdhc1 {
>  	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>  	bus-width = <8>;
>  	non-removable;
> +	fsl,tuning-step = <1>;
>  	status = "okay";
>  };
>
> @@ -519,6 +520,7 @@ &usdhc2 {
>  	vmmc-supply = <&reg_usdhc2_vmmc>;
>  	bus-width = <4>;
>  	no-mmc;
> +	fsl,tuning-step = <1>;
>  	status = "okay";
>  };
>
> --
> 2.34.1
>

Re: [PATCH v2 1/3] arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD

[Peng Fan]

On Thu, Jan 29, 2026 at 04:04:37PM +0800, ziniu.wang_1@nxp.com wrote:
>From: Luke Wang <ziniu.wang_1@nxp.com>
>
>During system resume, the following errors occurred:
>
>  [  430.638625] mmc1: error -84 writing Cache Enable bit
>  [  430.643618] mmc1: error -84 doing runtime resume
>
>For eMMC and SD, there are two tuning pass windows and the gap between
>those two windows may only have one cell. If tuning step > 1, the gap may
>just be skipped and host assumes those two windows as a continuous
>windows. This will cause a wrong delay cell near the gap to be selected.
>
>Set the tuning step to 1 to avoid selecting the wrong delay cell.
>
>For SDIO, the gap is sufficiently large, so the default tuning step does
>not cause this issue.

Adding a fix tag? one more question, I see all three patches are all
changing to 1, could this change be in imx91_93_common.dtsi?

Regards
Peng

>
>Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
>---
> arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
>index 0852067eab2c..197c8f8b7f66 100644
>--- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
>+++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
>@@ -507,6 +507,7 @@ &usdhc1 {
> 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> 	bus-width = <8>;
> 	non-removable;
>+	fsl,tuning-step = <1>;
> 	status = "okay";
> };
> 
>@@ -519,6 +520,7 @@ &usdhc2 {
> 	vmmc-supply = <&reg_usdhc2_vmmc>;
> 	bus-width = <4>;
> 	no-mmc;
>+	fsl,tuning-step = <1>;
> 	status = "okay";
> };
> 
>-- 
>2.34.1
>

RE: [PATCH v2 1/3] arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD

[Luke Wang]

> -----Original Message-----
> From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> Sent: Monday, February 2, 2026 11:40 AM
> To: Luke Wang <ziniu.wang_1@nxp.com>
> Cc: shawnguo@kernel.org; s.hauer@pengutronix.de; Frank Li
> <frank.li@nxp.com>; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; kernel@pengutronix.de; festevam@gmail.com;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 1/3] arm64: dts: imx93-9x9-qsb: change usdhc tuning
> step for eMMC and SD
> 
> On Thu, Jan 29, 2026 at 04:04:37PM +0800, ziniu.wang_1@nxp.com wrote:
> >From: Luke Wang <ziniu.wang_1@nxp.com>
> >
> >During system resume, the following errors occurred:
> >
> >  [  430.638625] mmc1: error -84 writing Cache Enable bit
> >  [  430.643618] mmc1: error -84 doing runtime resume
> >
> >For eMMC and SD, there are two tuning pass windows and the gap between
> >those two windows may only have one cell. If tuning step > 1, the gap may
> >just be skipped and host assumes those two windows as a continuous
> >windows. This will cause a wrong delay cell near the gap to be selected.
> >
> >Set the tuning step to 1 to avoid selecting the wrong delay cell.
> >
> >For SDIO, the gap is sufficiently large, so the default tuning step does
> >not cause this issue.
> 
> Adding a fix tag? one more question, I see all three patches are all
> changing to 1, could this change be in imx91_93_common.dtsi?

Will add fix tag in next version.
Tuning timing is related to board design. Costumer board may not need
to change to 1 if the gap is sufficiently large.

Regards,
Luke

> 
> Regards
> Peng
> 
> >
> >Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
> >---
> > arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> >diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> >index 0852067eab2c..197c8f8b7f66 100644
> >--- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> >+++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
> >@@ -507,6 +507,7 @@ &usdhc1 {
> > 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> > 	bus-width = <8>;
> > 	non-removable;
> >+	fsl,tuning-step = <1>;
> > 	status = "okay";
> > };
> >
> >@@ -519,6 +520,7 @@ &usdhc2 {
> > 	vmmc-supply = <&reg_usdhc2_vmmc>;
> > 	bus-width = <4>;
> > 	no-mmc;
> >+	fsl,tuning-step = <1>;
> > 	status = "okay";
> > };
> >
> >--
> >2.34.1
> >