From: Niklas Cassel <cassel@kernel.org>
To: Grimmauld <grimmauld@grimmauld.de>
Cc: "Anand Moon" <linux.amoon@gmail.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Enable async probe by default
Date: Mon, 2 Feb 2026 11:02:09 +0100 [thread overview]
Message-ID: <aYB2IVdh_kth1wtn@ryzen> (raw)
In-Reply-To: <aXyHITrZ89Mmn8_J@ryzen>
On Fri, Jan 30, 2026 at 11:25:37AM +0100, Niklas Cassel wrote:
> Note that I've built the network PHY driver that phylib wants to load
> (CONFIG_REALTEK_PHY=y) as built-in. As long as the PHY driver is built
> as built-in, I don't think that the problem the modules code is warning
> about can happen. (But I also don't understand why it is trying to load
> a module when the driver is built as built-in in the first place...)
FWIW, the reason why PHYLIB tries to load the module even though it is built
as built-in (i.e. is already loaded) is explained by the following comment:
https://github.com/torvalds/linux/blob/v6.19-rc8/drivers/net/phy/phy_device.c#L852-L855
Kind regards,
Niklas
next prev parent reply other threads:[~2026-02-02 10:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-09 7:36 [PATCH v2] PCI: dw-rockchip: Enable async probe by default Anand Moon
2025-01-03 11:31 ` Niklas Cassel
2025-01-03 13:54 ` Anand Moon
2025-01-03 14:25 ` Niklas Cassel
2025-01-03 14:40 ` Anand Moon
2025-01-03 14:45 ` Niklas Cassel
2025-01-03 15:06 ` Anand Moon
2025-01-03 15:10 ` Niklas Cassel
2025-01-03 15:29 ` Anand Moon
2025-01-03 15:45 ` Niklas Cassel
2025-01-05 16:35 ` Manivannan Sadhasivam
2025-01-05 17:46 ` Anand Moon
2025-01-03 16:04 ` Andrew Lunn
2025-01-05 17:46 ` Anand Moon
2025-01-05 17:57 ` Andrew Lunn
2025-01-06 7:58 ` Anand Moon
2025-01-06 12:02 ` Niklas Cassel
2025-01-06 13:44 ` Andrew Lunn
2025-01-07 11:13 ` Anand Moon
2025-01-07 13:13 ` Andrew Lunn
2025-01-07 14:57 ` Anand Moon
2025-01-15 17:49 ` Manivannan Sadhasivam
2026-01-29 14:06 ` Grimmauld
2026-01-30 10:25 ` Niklas Cassel
2026-01-31 9:38 ` Anand Moon
2026-02-02 9:54 ` Niklas Cassel
2026-02-02 18:05 ` Anand Moon
2026-02-03 11:01 ` Niklas Cassel
2026-02-02 10:02 ` Niklas Cassel [this message]
2026-02-02 18:07 ` Anand Moon
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