From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: <dan.j.williams@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>,
"Jonathan Cameron" <jonathan.cameron@huawei.com>,
"will@kernel.org" <will@kernel.org>,
"robin.murphy@arm.com" <robin.murphy@arm.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"joro@8bytes.org" <joro@8bytes.org>,
"praan@google.com" <praan@google.com>,
"baolu.lu@linux.intel.com" <baolu.lu@linux.intel.com>,
"miko.lenczewski@arm.com" <miko.lenczewski@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices
Date: Tue, 3 Feb 2026 09:45:17 -0800 [thread overview]
Message-ID: <aYI0LUdXqrjmRcMo@Asurada-Nvidia> (raw)
In-Reply-To: <20260203143348.GA3931454@nvidia.com>
On Tue, Feb 03, 2026 at 10:33:48AM -0400, Jason Gunthorpe wrote:
> On Mon, Feb 02, 2026 at 09:13:50PM -0800, Nicolin Chen wrote:
> > On Wed, Jan 28, 2026 at 09:05:20AM -0400, Jason Gunthorpe wrote:
> > > On Tue, Jan 27, 2026 at 04:49:07PM -0800, dan.j.williams@intel.com wrote:
> > > > > Yes, ARM took the position that ATS should be left disabled for
> > > > > IDENTITY both because of SMMU constraints and also because it made
> > > > > some sense that you wouldn't want ATS overhead just to get a 1:1
> > > > > translation.
> > > >
> > > > Does this mean that ARM already today does not enable ATS until driver
> > > > attach, or is incremental work needed for that capability?
> > >
> > > All of the iommu drivers setup an iommu translation and enable ATS
> > > before any driver is bound.
> > >
> > > We would need to do more work in the core to leave the translation
> > > blocked when there is no driver. I don't think it is that difficult
> >
> > Hmm, not sure if we could use group->domain=NULL as "blocked..
>
> Definately not, we need to use a proper blocked domain.
Yea, I suspected so.
> > @@ -437,8 +437,6 @@ static int driver_sysfs_add(struct device *dev)
> > {
> > int ret;
> >
> > - bus_notify(dev, BUS_NOTIFY_BIND_DRIVER);
> > -
> > ret = sysfs_create_link(&dev->driver->p->kobj, &dev->kobj,
> > kobject_name(&dev->kobj));
> > if (ret)
> > @@ -638,10 +636,12 @@ static int really_probe(struct device *dev, const struct device_driver *drv)
> > if (ret)
> > goto pinctrl_bind_failed;
> >
> > + bus_notify(dev, BUS_NOTIFY_BIND_DRIVER);
> > +
> > if (dev->bus->dma_configure) {
> > ret = dev->bus->dma_configure(dev);
> > if (ret)
> > - goto pinctrl_bind_failed;
> > + goto bus_notify_bind_failed;
> > }
>
> We shouldn't need any of these? The dma_configure callback already
> gets into the iommu code to validate the domain and restrict VFIO,
> no further callbacks should be needed.
>
> When the iommu driver is probed to the device we can assume no driver
> is bound and immediately attach the blocked domain.
I was trying to use dev->driver that gets set before dma_configure()
and unset after dma_cleanup(). But looks like we could just keep the
track of group->owner_cnt in iommu_device_use/unuse_default_domain().
Btw, attaching to IOMMU_DOMAIN_BLOCKED/group->blocking_domain is not
allowed in general if require_direct=true. I assume this case can be
an exception since there's no point in allowing a device that has no
driver yet to access any reserved region?
Thanks
Nicolin
next prev parent reply other threads:[~2026-02-03 17:45 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-17 4:56 [PATCH RFCv1 0/3] Allow ATS to be always on for certain ATS-capable devices Nicolin Chen
2026-01-17 4:56 ` [PATCH RFCv1 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices Nicolin Chen
2026-01-19 17:58 ` Jason Gunthorpe
2026-01-21 8:01 ` Tian, Kevin
2026-01-21 10:03 ` Jonathan Cameron
2026-01-21 13:03 ` Jason Gunthorpe
2026-01-22 1:17 ` Baolu Lu
2026-01-22 13:15 ` Jason Gunthorpe
2026-01-22 5:44 ` dan.j.williams
2026-01-22 13:14 ` Jason Gunthorpe
2026-01-22 16:29 ` Nicolin Chen
2026-01-22 16:58 ` Jason Gunthorpe
2026-01-22 19:46 ` dan.j.williams
2026-01-27 8:10 ` Tian, Kevin
2026-01-27 15:04 ` Jason Gunthorpe
2026-01-28 0:49 ` dan.j.williams
2026-01-28 13:05 ` Jason Gunthorpe
2026-02-03 5:13 ` Nicolin Chen
2026-02-03 14:33 ` Jason Gunthorpe
2026-02-03 17:45 ` Nicolin Chen [this message]
2026-02-03 17:55 ` Jason Gunthorpe
2026-02-03 18:50 ` Nicolin Chen
2026-02-04 13:21 ` Jason Gunthorpe
2026-02-03 18:59 ` Robin Murphy
2026-02-03 19:24 ` Nicolin Chen
2026-02-03 23:16 ` Jason Gunthorpe
2026-02-04 12:18 ` Robin Murphy
2026-02-04 13:20 ` Jason Gunthorpe
2026-02-18 22:56 ` Nicolin Chen
2026-02-19 14:37 ` Jason Gunthorpe
2026-02-19 16:53 ` Nicolin Chen
2026-02-19 17:41 ` Jason Gunthorpe
2026-02-20 4:52 ` Nicolin Chen
2026-02-20 12:50 ` Jason Gunthorpe
2026-02-20 13:22 ` Robin Murphy
2026-02-20 13:51 ` Jason Gunthorpe
2026-02-20 14:45 ` Robin Murphy
2026-02-26 15:10 ` Jason Gunthorpe
2026-02-20 18:49 ` Nicolin Chen
2026-02-24 14:38 ` Jason Gunthorpe
2026-01-28 0:57 ` Tian, Kevin
2026-01-28 13:11 ` Jason Gunthorpe
2026-01-29 3:28 ` Tian, Kevin
2026-01-22 10:24 ` Alejandro Lucero Palau
2026-01-17 4:56 ` [PATCH RFCv1 2/3] PCI: Allow ATS to be always on for non-CXL NVIDIA GPUs Nicolin Chen
2026-01-19 18:00 ` Jason Gunthorpe
2026-01-19 18:09 ` Nicolin Chen
2026-01-17 4:56 ` [PATCH RFCv1 3/3] iommu/arm-smmu-v3: Allow ATS to be always on Nicolin Chen
2026-01-19 20:06 ` Jason Gunthorpe
2026-01-26 12:39 ` Will Deacon
2026-01-26 17:20 ` Jason Gunthorpe
2026-01-26 18:40 ` Nicolin Chen
2026-01-26 19:16 ` Jason Gunthorpe
2026-01-26 18:49 ` Robin Murphy
2026-01-26 19:09 ` Jason Gunthorpe
2026-01-27 13:10 ` Will Deacon
2026-01-27 13:26 ` Robin Murphy
2026-01-27 13:50 ` Will Deacon
2026-01-27 14:49 ` Jason Gunthorpe
2026-01-26 18:21 ` Nicolin Chen
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