Re: [External] [PATCH RFC v2 16/17] acpi: riscv: Parse RISC-V Quality of Service Controller (RQSC) table

[Drew Fustini <fustini@kernel.org>]

On Mon, Feb 02, 2026 at 07:08:48PM +0800, yunhui cui wrote:
> Hi Drew,
> 
> On Thu, Jan 29, 2026 at 4:28 AM Drew Fustini <fustini@kernel.org> wrote:
> >
> > Add driver to parse the ACPI RISC-V Quality of Service Controller (RQSC)
> > table which describes the capacity and bandwidth QoS controllers in a
> > system. The QoS controllers implement the RISC-V Capacity and Bandwidth
> > Controller QoS Register Interface (CBQRI) specification.
> >
> > Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0
> > Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > ---
> >  MAINTAINERS                   |   1 +
> >  arch/riscv/include/asm/acpi.h |  10 ++++
> >  drivers/acpi/riscv/Makefile   |   2 +-
> >  drivers/acpi/riscv/rqsc.c     | 112 ++++++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 124 insertions(+), 1 deletion(-)
> >
[..]
> > +int acpi_parse_rqsc(struct acpi_table_header *table)
> > +{
> > +       struct acpi_table_rqsc *rqsc;
> > +       int err;
> > +
> > +       BUG_ON(acpi_disabled);
> > +       if (!table) {
> > +               rqsc = acpi_get_rqsc();
> > +               if (!rqsc)
> > +                       return -ENOENT;
> > +       } else {
> > +               rqsc = (struct acpi_table_rqsc *)table;
> > +       }
> > +
> > +       for (int i = 0; i < rqsc->num; i++) {
> > +               struct cbqri_controller_info *ctrl_info;
> > +
> > +               ctrl_info = kzalloc(sizeof(*ctrl_info), GFP_KERNEL);
> > +               if (!ctrl_info)
> > +                       return -ENOMEM;
> > +
> > +               ctrl_info->type = rqsc->f[i].type;
> > +               ctrl_info->addr = rqsc->f[i].reg[1];
> > +               ctrl_info->size = CBQRI_CTRL_SIZE;
> > +               ctrl_info->rcid_count = rqsc->f[i].rcid;
> > +               ctrl_info->mcid_count = rqsc->f[i].mcid;
> > +
> > +               pr_info("Found controller with type %u addr 0x%lx size  %lu rcid  %u mcid  %u",
> > +                       ctrl_info->type, ctrl_info->addr, ctrl_info->size,
> > +                       ctrl_info->rcid_count, ctrl_info->mcid_count);
> > +
> > +               if (ctrl_info->type == CBQRI_CONTROLLER_TYPE_CAPACITY) {
> > +                       ctrl_info->cache.cache_id = rqsc->f[i].res.id1;
> > +                       ctrl_info->cache.cache_level =
> > +                               find_acpi_cache_level_from_id(ctrl_info->cache.cache_id);
> > +
> > +                       struct acpi_pptt_cache *cache;
> > +
> > +                       cache = find_acpi_cache_from_id(ctrl_info->cache.cache_id);
> > +                       if (cache) {
> > +                               ctrl_info->cache.cache_size = cache->size;
> > +                       } else {
> > +                               pr_warn("%s(): failed to determine size for cache id 0x%x",
> > +                                       __func__, ctrl_info->cache.cache_id);
> > +                               ctrl_info->cache.cache_size = 0;
> > +                       }
> > +
> > +                       pr_info("Cache controller has ID 0x%x level %u size %u ",
> > +                               ctrl_info->cache.cache_id, ctrl_info->cache.cache_level,
> > +                               ctrl_info->cache.cache_size);
> > +
> > +                       /*
> > +                        * For CBQRI, any cpu (technically a hart in RISC-V terms)
> > +                        * can access the memory-mapped registers of any CBQRI
> > +                        * controller in the system.
> > +                        */
> > +                       err = cpumask_parse("FF", &ctrl_info->cache.cpu_mask);
> 
> Hardcode? acpi_pptt_get_cpumask_from_cache_id(ctrl_info->cache.cache_id,
> &ctrl_info->cache.cpu_mask); ?

Thanks, I will give that a try as the current value 0xFF is not flexible.

Drew