Re: [PATCH v3 07/26] x86/virt/seamldr: Introduce a wrapper for P-SEAMLDR SEAMCALLs

[Chao Gao <chao.gao@intel.com>]

>On Fri, Jan 30, 2026 at 8:23 AM Dave Hansen <dave.hansen@intel.com> wrote:
>> On 1/30/26 00:08, Chao Gao wrote:
>> > AFAIK, this is a CPU implementation issue. The actual requirement is to
>> > evict (flush and invalidate) all VMCSs __cached in SEAM mode__, but big
>> > cores implement this by evicting the __entire__ VMCS cache. So, the
>> > current VMCS is invalidated and cleared.
>>
>> But why is this a P-SEAMLDR thing and not a TDX module thing?
>
>My guess is that it's because the P-SEAMLDR code loads and prepares the new TDX-
>Module by constructing the VMCS used for SEAMCALL using direct writes to memory
>(unless that TDX behavior has changed in the last few years).  And so it needs
>to ensure that in-memory representation is synchronized with the VMCS cache.
>
>Hmm, but that doesn't make sense _if_ it really truly is SEAMRET that does the VMCS
>cache invalidation, because flushing the VMCS cache would ovewrite the in-memory
>state.

My understanding is:

1. SEAMCALL/SEAMRET use VMCSs.

2. P-SEAMLDR is single-threaded (likely for simplicity). So, it uses a _single_
   global VMCS and only one CPU can call P-SEAMLDR calls at a time.

3. After SEAMRET from P-SEAMLDR, _if_ the global VMCS isn't flushed, other CPUs
   cannot enter P-SEAMLDR because the global VMCS would be corrupted. (note the
   global VMCS is cached by the original CPU).

4. To make P-SEAMLDR callable on all CPUs, SEAMRET instruction flush VMCSs.
   The flush cannot be performed by the host VMM since the global VMCS is not
   visible to it. P-SEAMLDR cannot do it either because SEAMRET is its final
   instruction and requires a valid VMCS.

The TDX Module has per-CPU VMCSs, so it doesn't has this problem.

I'll check if SEAM ISA architects can join to explain this in more detail.

>
>> It seems like a bug, or at least a P-SEAMLDR implementation issue the
>> needs to get fixed.
>
>Yeah, 'tis odd behavior.  IMO, that's all the more reason the TDX subsystem should
>hide the quirk from the rest of the kernel.
>
>[*] https://lore.kernel.org/all/20251010220403.987927-1-seanjc@google.com