[PATCH RESEND 0/5] KVM: x86: selftests: Add Hygon CPUs support and fix failures

[PATCH RESEND 0/5] KVM: x86: selftests: Add Hygon CPUs support and fix failures

[Zhiquan Li]

This series to add support for Hygon CPUs and fix 11 KVM selftest failures
on Hygon architecture.

Patch 1 add CPU vendor detection for Hygon and add a global variable
"host_cpu_is_hygon" to identify if the test is running on a Hygon CPU.
It is the prerequisite for the following fixes.

Patch 2 fix x86/fix_hypercall_test test failure by altering the hypercall
instruction on Hygon CPUs.

Patch 3 fix following test failures by avoiding using the reserved
memory regions on Hygon CPUs.
- access_tracking_perf_test
- demand_paging_test
- dirty_log_perf_test
- dirty_log_test
- kvm_page_table_test
- memslot_modification_stress_test
- pre_fault_memory_test
- x86/dirty_log_page_splitting_test

Patch 4 fix x86/pmu_event_filter_test test failure by allowing the tests
for Hygon CPUs.

Patch 5 fix x86/msrs_test test failure by fixing the expectation while
writing the MSR_TSC_AUX reserved bits without RDPID support.

Zhiquan Li (5):
  KVM: x86: selftests: Add CPU vendor detection for Hygon
  KVM: x86: selftests: Alter the instruction of hypercall on Hygon
  KVM: x86: selftests: Avoid failures due to reserved memory address
    regions on Hygon
  KVM: x86: selftests: Allow the PMU event filter test for Hygon
  KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure
    on Hygon

 .../selftests/kvm/include/x86/processor.h     |  6 +++++
 .../testing/selftests/kvm/lib/x86/processor.c | 12 ++++++---
 .../selftests/kvm/x86/fix_hypercall_test.c    |  2 +-
 tools/testing/selftests/kvm/x86/msrs_test.c   | 26 +++++++++++++++----
 .../selftests/kvm/x86/pmu_event_filter_test.c |  6 ++---
 5 files changed, 39 insertions(+), 13 deletions(-)


base-commit: 05f7e89ab9731565d8a62e3b5d1ec206485eeb0b

---
Re-send: rebase to v6.19

-- 
2.43.0

[PATCH RESEND 1/5] KVM: x86: selftests: Add CPU vendor detection for Hygon

[Zhiquan Li]

Currently some KVM selftests are failed on Hygon CPUs due to missing
vendor detection and edge-case handling specific to Hygon's
architecture.

Add CPU vendor detection for Hygon and add a global variable
"host_cpu_is_hygon" as the basic facility for the following fixes.

Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
---
 tools/testing/selftests/kvm/include/x86/processor.h | 6 ++++++
 tools/testing/selftests/kvm/lib/x86/processor.c     | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h
index 57d62a425109..9ac18e0fca54 100644
--- a/tools/testing/selftests/kvm/include/x86/processor.h
+++ b/tools/testing/selftests/kvm/include/x86/processor.h
@@ -21,6 +21,7 @@
 
 extern bool host_cpu_is_intel;
 extern bool host_cpu_is_amd;
+extern bool host_cpu_is_hygon;
 extern uint64_t guest_tsc_khz;
 
 #ifndef MAX_NR_CPUID_ENTRIES
@@ -701,6 +702,11 @@ static inline bool this_cpu_is_amd(void)
 	return this_cpu_vendor_string_is("AuthenticAMD");
 }
 
+static inline bool this_cpu_is_hygon(void)
+{
+	return this_cpu_vendor_string_is("HygonGenuine");
+}
+
 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index,
 				      uint8_t reg, uint8_t lo, uint8_t hi)
 {
diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index 36104d27f3d9..bbd3336f22eb 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -21,6 +21,7 @@
 vm_vaddr_t exception_handlers;
 bool host_cpu_is_amd;
 bool host_cpu_is_intel;
+bool host_cpu_is_hygon;
 bool is_forced_emulation_enabled;
 uint64_t guest_tsc_khz;
 
@@ -671,6 +672,7 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus)
 
 	sync_global_to_guest(vm, host_cpu_is_intel);
 	sync_global_to_guest(vm, host_cpu_is_amd);
+	sync_global_to_guest(vm, host_cpu_is_hygon);
 	sync_global_to_guest(vm, is_forced_emulation_enabled);
 	sync_global_to_guest(vm, pmu_errata_mask);
 
@@ -1303,6 +1305,7 @@ void kvm_selftest_arch_init(void)
 {
 	host_cpu_is_intel = this_cpu_is_intel();
 	host_cpu_is_amd = this_cpu_is_amd();
+	host_cpu_is_hygon = this_cpu_is_hygon();
 	is_forced_emulation_enabled = kvm_is_forced_emulation_enabled();
 
 	kvm_init_pmu_errata();
-- 
2.43.0

[PATCH RESEND 2/5] KVM: x86: selftests: Alter the instruction of hypercall on Hygon

[Zhiquan Li]

Hygon architecture uses VMMCALL as guest hypercall instruction.  Now,
the test like "fix hypercall" uses VMCALL and then results in test
failure.

Utilize the Hygon-specific flag to identify if the test is running on
Hygon CPU and alter the instruction of hypercall if needed.

Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
---
 tools/testing/selftests/kvm/lib/x86/processor.c      | 3 ++-
 tools/testing/selftests/kvm/x86/fix_hypercall_test.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index bbd3336f22eb..64f9ecd2387d 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -1229,7 +1229,8 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
 		     "1: vmmcall\n\t"					\
 		     "2:"						\
 		     : "=a"(r)						\
-		     : [use_vmmcall] "r" (host_cpu_is_amd), inputs);	\
+		     : [use_vmmcall] "r"				\
+		     (host_cpu_is_amd || host_cpu_is_hygon), inputs);	\
 									\
 	r;								\
 })
diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
index 762628f7d4ba..0377ab5b1238 100644
--- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
+++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
@@ -52,7 +52,7 @@ static void guest_main(void)
 	if (host_cpu_is_intel) {
 		native_hypercall_insn = vmx_vmcall;
 		other_hypercall_insn  = svm_vmmcall;
-	} else if (host_cpu_is_amd) {
+	} else if (host_cpu_is_amd || host_cpu_is_hygon) {
 		native_hypercall_insn = svm_vmmcall;
 		other_hypercall_insn  = vmx_vmcall;
 	} else {
-- 
2.43.0

[PATCH RESEND 3/5] KVM: x86: selftests: Avoid failures due to reserved memory address regions on Hygon

[Zhiquan Li]

There are similar reserved memory address regions for Hygon
architecture, mapping memory into these regions and accessing to them
results in a #PF.

Hygon CSV also makes the "physical address space width reduction", the
reduced physical address bits are reported by bits 11:6 of
CPUID[0x8000001f].EBX as well, so the existed logic is totally
applicable for Hygon processors.

Following test failures are fixed by this change:
- access_tracking_perf_test
- demand_paging_test
- dirty_log_perf_test
- dirty_log_test
- kvm_page_table_test
- memslot_modification_stress_test
- pre_fault_memory_test
- x86/dirty_log_page_splitting_test

Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
---
 tools/testing/selftests/kvm/lib/x86/processor.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index 64f9ecd2387d..252b04c8e944 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -1270,8 +1270,8 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm)
 
 	max_gfn = (1ULL << (guest_maxphyaddr - vm->page_shift)) - 1;
 
-	/* Avoid reserved HyperTransport region on AMD processors.  */
-	if (!host_cpu_is_amd)
+	/* Avoid reserved HyperTransport region on AMD or Hygon processors. */
+	if (!host_cpu_is_amd && !host_cpu_is_hygon)
 		return max_gfn;
 
 	/* On parts with <40 physical address bits, the area is fully hidden */
@@ -1285,7 +1285,7 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm)
 
 	/*
 	 * Otherwise it's at the top of the physical address space, possibly
-	 * reduced due to SME by bits 11:6 of CPUID[0x8000001f].EBX.  Use
+	 * reduced due to SME or CSV by bits 11:6 of CPUID[0x8000001f].EBX.  Use
 	 * the old conservative value if MAXPHYADDR is not enumerated.
 	 */
 	if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR))
-- 
2.43.0

[PATCH RESEND 4/5] KVM: x86: selftests: Allow the PMU event filter test for Hygon

[Zhiquan Li]

At present, the PMU event filter test is only available for Intel and
AMD architecture conditionally, but it is applicable for Hygon
architecture as well.

Since all known Hygon processors can re-use the test cases, so it isn't
necessary to create a wrapper like other architectures, using the
"host_cpu_is_hygon" variable should be enough.

Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
---
 tools/testing/selftests/kvm/x86/pmu_event_filter_test.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
index 1c5b7611db24..e6badd9a2a2a 100644
--- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
+++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
@@ -842,14 +842,14 @@ int main(int argc, char *argv[])
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_PMU_EVENT_FILTER));
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_PMU_EVENT_MASKED_EVENTS));
 
-	TEST_REQUIRE(use_intel_pmu() || use_amd_pmu());
+	TEST_REQUIRE(use_intel_pmu() || use_amd_pmu() || host_cpu_is_hygon);
 	guest_code = use_intel_pmu() ? intel_guest_code : amd_guest_code;
 
 	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
 
 	TEST_REQUIRE(sanity_check_pmu(vcpu));
 
-	if (use_amd_pmu())
+	if (use_amd_pmu() || host_cpu_is_hygon)
 		test_amd_deny_list(vcpu);
 
 	test_without_filter(vcpu);
@@ -862,7 +862,7 @@ int main(int argc, char *argv[])
 	    supports_event_mem_inst_retired() &&
 	    kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS) >= 3)
 		vcpu2 = vm_vcpu_add(vm, 2, intel_masked_events_guest_code);
-	else if (use_amd_pmu())
+	else if (use_amd_pmu() || host_cpu_is_hygon)
 		vcpu2 = vm_vcpu_add(vm, 2, amd_masked_events_guest_code);
 
 	if (vcpu2)
-- 
2.43.0

[PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Zhiquan Li]

On Hygon processors either RDTSCP or RDPID is supported in the host,
MSR_TSC_AUX is able to be accessed.

The write reserved bits test for MSR_TSC_AUX while RDPID as "feature"
and RDTSCP as "feature2" is failed on Hygon CPUs which only support
RDTSCP but not support RDPID.  In current design, if RDPID is not
supported, vCPU0 and vCPU1 write reserved bits expects #GP, however, it
is not applicable for Hygon CPUs.  Since on Hygon architecture whether
or not RDPID is supported in the host, once RDTSCP is supported,
MSR_TSC_AUX is able to be accessed, vCPU0 and vCPU1 drop bits 63:32 and
write successfully.

Therefore, the expectation of writing MSR_TSC_AUX reserved bits on Hygon
CPUs should be:
1) either RDTSCP or RDPID is supported case, and both are supported
   case, expect success and a truncated value, not #GP.
2) neither RDTSCP nor RDPID is supported, expect #GP.

Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
---
 tools/testing/selftests/kvm/x86/msrs_test.c | 26 +++++++++++++++++----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
index 40d918aedce6..2f1e800fe691 100644
--- a/tools/testing/selftests/kvm/x86/msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/msrs_test.c
@@ -77,11 +77,11 @@ static bool ignore_unsupported_msrs;
 static u64 fixup_rdmsr_val(u32 msr, u64 want)
 {
 	/*
-	 * AMD CPUs drop bits 63:32 on some MSRs that Intel CPUs support.  KVM
-	 * is supposed to emulate that behavior based on guest vendor model
+	 * AMD and Hygon CPUs drop bits 63:32 on some MSRs that Intel CPUs support.
+	 * KVM is supposed to emulate that behavior based on guest vendor model
 	 * (which is the same as the host vendor model for this test).
 	 */
-	if (!host_cpu_is_amd)
+	if (!host_cpu_is_amd && !host_cpu_is_hygon)
 		return want;
 
 	switch (msr) {
@@ -94,6 +94,17 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want)
 	}
 }
 
+/*
+ * On Hygon processors either RDTSCP or RDPID is supported in the host,
+ * MSR_TSC_AUX is able to be accessed.
+ */
+static bool is_hygon_msr_tsc_aux_supported(const struct kvm_msr *msr)
+{
+	return host_cpu_is_hygon &&
+			msr->index == MSR_TSC_AUX &&
+			(this_cpu_has(msr->feature) || this_cpu_has(msr->feature2));
+}
+
 static void __rdmsr(u32 msr, u64 want)
 {
 	u64 val;
@@ -174,9 +185,14 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
 	/*
 	 * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
 	 * expect success and a truncated value, not #GP.
+	 *
+	 * On Hygon CPUs whether or not RDPID is supported in the host, once RDTSCP
+	 * is supported, MSR_TSC_AUX is able to be accessed.  So, for either RDTSCP
+	 * or RDPID is supported case and both are supported case, expect
+	 * success and a truncated value, not #GP.
 	 */
-	if (!this_cpu_has(msr->feature) ||
-	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
+	if (!is_hygon_msr_tsc_aux_supported(msr) && (!this_cpu_has(msr->feature) ||
+	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val))) {
 		u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
 
 		__GUEST_ASSERT(vec == GP_VECTOR,
-- 
2.43.0

Re: [PATCH RESEND 2/5] KVM: x86: selftests: Alter the instruction of hypercall on Hygon

[Sean Christopherson]

On Mon, Feb 09, 2026, Zhiquan Li wrote:
> Hygon architecture uses VMMCALL as guest hypercall instruction.  Now,
> the test like "fix hypercall" uses VMCALL and then results in test
> failure.
> 
> Utilize the Hygon-specific flag to identify if the test is running on
> Hygon CPU and alter the instruction of hypercall if needed.
> 
> Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
> ---
>  tools/testing/selftests/kvm/lib/x86/processor.c      | 3 ++-
>  tools/testing/selftests/kvm/x86/fix_hypercall_test.c | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
> index bbd3336f22eb..64f9ecd2387d 100644
> --- a/tools/testing/selftests/kvm/lib/x86/processor.c
> +++ b/tools/testing/selftests/kvm/lib/x86/processor.c
> @@ -1229,7 +1229,8 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
>  		     "1: vmmcall\n\t"					\
>  		     "2:"						\
>  		     : "=a"(r)						\
> -		     : [use_vmmcall] "r" (host_cpu_is_amd), inputs);	\
> +		     : [use_vmmcall] "r"				\
> +		     (host_cpu_is_amd || host_cpu_is_hygon), inputs);	\

Rather than play a constant game of whack-a-mole and end up with a huge number of
"host_cpu_is_amd || host_cpu_is_hygon" checks, I would prefer to add (in addition
to host_cpu_is_hygon) a "host_cpu_is_amd_compatible" flag.

E.g. slotted in after patch 1, something like this:

---
 tools/testing/selftests/kvm/include/x86/processor.h  | 1 +
 tools/testing/selftests/kvm/lib/x86/processor.c      | 8 ++++++--
 tools/testing/selftests/kvm/x86/fix_hypercall_test.c | 2 +-
 tools/testing/selftests/kvm/x86/msrs_test.c          | 2 +-
 tools/testing/selftests/kvm/x86/xapic_state_test.c   | 2 +-
 5 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h
index 1338de7111e7..40e3deb64812 100644
--- a/tools/testing/selftests/kvm/include/x86/processor.h
+++ b/tools/testing/selftests/kvm/include/x86/processor.h
@@ -22,6 +22,7 @@
 extern bool host_cpu_is_intel;
 extern bool host_cpu_is_amd;
 extern bool host_cpu_is_hygon;
+extern bool host_cpu_is_amd_compatible;
 extern uint64_t guest_tsc_khz;
 
 #ifndef MAX_NR_CPUID_ENTRIES
diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index f6b1c5324931..7b7fd2ad148f 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -24,6 +24,7 @@ vm_vaddr_t exception_handlers;
 bool host_cpu_is_amd;
 bool host_cpu_is_intel;
 bool host_cpu_is_hygon;
+bool host_cpu_is_amd_compatible;
 bool is_forced_emulation_enabled;
 uint64_t guest_tsc_khz;
 
@@ -794,6 +795,7 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus)
 	sync_global_to_guest(vm, host_cpu_is_intel);
 	sync_global_to_guest(vm, host_cpu_is_amd);
 	sync_global_to_guest(vm, host_cpu_is_hygon);
+	sync_global_to_guest(vm, host_cpu_is_amd_compatible);
 	sync_global_to_guest(vm, is_forced_emulation_enabled);
 	sync_global_to_guest(vm, pmu_errata_mask);
 
@@ -1350,7 +1352,8 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
 		     "1: vmmcall\n\t"					\
 		     "2:"						\
 		     : "=a"(r)						\
-		     : [use_vmmcall] "r" (host_cpu_is_amd), inputs);	\
+		     : [use_vmmcall] "r" (host_cpu_is_amd_compatible),	\
+		       inputs);						\
 									\
 	r;								\
 })
@@ -1391,7 +1394,7 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm)
 	max_gfn = (1ULL << (guest_maxphyaddr - vm->page_shift)) - 1;
 
 	/* Avoid reserved HyperTransport region on AMD processors.  */
-	if (!host_cpu_is_amd)
+	if (!host_cpu_is_amd_compatible)
 		return max_gfn;
 
 	/* On parts with <40 physical address bits, the area is fully hidden */
@@ -1427,6 +1430,7 @@ void kvm_selftest_arch_init(void)
 	host_cpu_is_intel = this_cpu_is_intel();
 	host_cpu_is_amd = this_cpu_is_amd();
 	host_cpu_is_hygon = this_cpu_is_hygon();
+	host_cpu_is_amd_compatible = host_cpu_is_amd || host_cpu_is_hygon;
 	is_forced_emulation_enabled = kvm_is_forced_emulation_enabled();
 
 	kvm_init_pmu_errata();
diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
index 762628f7d4ba..00b6e85735dd 100644
--- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
+++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
@@ -52,7 +52,7 @@ static void guest_main(void)
 	if (host_cpu_is_intel) {
 		native_hypercall_insn = vmx_vmcall;
 		other_hypercall_insn  = svm_vmmcall;
-	} else if (host_cpu_is_amd) {
+	} else if (host_cpu_is_amd_compatible) {
 		native_hypercall_insn = svm_vmmcall;
 		other_hypercall_insn  = vmx_vmcall;
 	} else {
diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
index 40d918aedce6..4c97444fdefe 100644
--- a/tools/testing/selftests/kvm/x86/msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/msrs_test.c
@@ -81,7 +81,7 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want)
 	 * is supposed to emulate that behavior based on guest vendor model
 	 * (which is the same as the host vendor model for this test).
 	 */
-	if (!host_cpu_is_amd)
+	if (!host_cpu_is_amd_compatible)
 		return want;
 
 	switch (msr) {
diff --git a/tools/testing/selftests/kvm/x86/xapic_state_test.c b/tools/testing/selftests/kvm/x86/xapic_state_test.c
index 3b4814c55722..0c5e12f5f14e 100644
--- a/tools/testing/selftests/kvm/x86/xapic_state_test.c
+++ b/tools/testing/selftests/kvm/x86/xapic_state_test.c
@@ -248,7 +248,7 @@ int main(int argc, char *argv[])
 	 * drops writes, AMD does not).  Account for the errata when checking
 	 * that KVM reads back what was written.
 	 */
-	x.has_xavic_errata = host_cpu_is_amd &&
+	x.has_xavic_errata = host_cpu_is_amd_compatible &&
 			     get_kvm_amd_param_bool("avic");
 
 	vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC);

base-commit: 391774310e7309b5a1ee12fac9264e95b1d4a6ee
--

Re: [PATCH RESEND 4/5] KVM: x86: selftests: Allow the PMU event filter test for Hygon

[Sean Christopherson]

On Mon, Feb 09, 2026, Zhiquan Li wrote:
> At present, the PMU event filter test is only available for Intel and
> AMD architecture conditionally, but it is applicable for Hygon
> architecture as well.
> 
> Since all known Hygon processors can re-use the test cases, so it isn't
> necessary to create a wrapper like other architectures, using the
> "host_cpu_is_hygon" variable should be enough.
> 
> Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
> ---
>  tools/testing/selftests/kvm/x86/pmu_event_filter_test.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
> index 1c5b7611db24..e6badd9a2a2a 100644
> --- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
> +++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
> @@ -842,14 +842,14 @@ int main(int argc, char *argv[])
>  	TEST_REQUIRE(kvm_has_cap(KVM_CAP_PMU_EVENT_FILTER));
>  	TEST_REQUIRE(kvm_has_cap(KVM_CAP_PMU_EVENT_MASKED_EVENTS));
>  
> -	TEST_REQUIRE(use_intel_pmu() || use_amd_pmu());
> +	TEST_REQUIRE(use_intel_pmu() || use_amd_pmu() || host_cpu_is_hygon);

Manually handling every check is rather silly, just do:

diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
index 1c5b7611db24..93b61c077991 100644
--- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
+++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
@@ -361,7 +361,8 @@ static bool use_intel_pmu(void)
  */
 static bool use_amd_pmu(void)
 {
-       return host_cpu_is_amd && kvm_cpu_family() >= 0x17;
+       return (host_cpu_is_amd && kvm_cpu_family() >= 0x17) ||
+              host_cpu_is_hygon;
 }
 
 /*

Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Sean Christopherson]

On Mon, Feb 09, 2026, Zhiquan Li wrote:
> Therefore, the expectation of writing MSR_TSC_AUX reserved bits on Hygon
> CPUs should be:
> 1) either RDTSCP or RDPID is supported case, and both are supported
>    case, expect success and a truncated value, not #GP.
> 2) neither RDTSCP nor RDPID is supported, expect #GP.

That's how Intel and AMD behave as well.  I don't understand why there needs to
be a big pile of special case code for Hygon.  Presumably just fixup_rdmsr_val()
needs to be changed?

> Signed-off-by: Zhiquan Li <zhiquan_li@163.com>
> ---
>  tools/testing/selftests/kvm/x86/msrs_test.c | 26 +++++++++++++++++----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
> index 40d918aedce6..2f1e800fe691 100644
> --- a/tools/testing/selftests/kvm/x86/msrs_test.c
> +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
> @@ -77,11 +77,11 @@ static bool ignore_unsupported_msrs;
>  static u64 fixup_rdmsr_val(u32 msr, u64 want)
>  {
>  	/*
> -	 * AMD CPUs drop bits 63:32 on some MSRs that Intel CPUs support.  KVM
> -	 * is supposed to emulate that behavior based on guest vendor model
> +	 * AMD and Hygon CPUs drop bits 63:32 on some MSRs that Intel CPUs support.
> +	 * KVM is supposed to emulate that behavior based on guest vendor model
>  	 * (which is the same as the host vendor model for this test).
>  	 */
> -	if (!host_cpu_is_amd)
> +	if (!host_cpu_is_amd && !host_cpu_is_hygon)
>  		return want;
>  
>  	switch (msr) {
> @@ -94,6 +94,17 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want)
>  	}
>  }
>  
> +/*
> + * On Hygon processors either RDTSCP or RDPID is supported in the host,
> + * MSR_TSC_AUX is able to be accessed.
> + */
> +static bool is_hygon_msr_tsc_aux_supported(const struct kvm_msr *msr)
> +{
> +	return host_cpu_is_hygon &&
> +			msr->index == MSR_TSC_AUX &&
> +			(this_cpu_has(msr->feature) || this_cpu_has(msr->feature2));

Align indentation, but as above, this shouldn't be necessary.

> +}
> +
>  static void __rdmsr(u32 msr, u64 want)
>  {
>  	u64 val;
> @@ -174,9 +185,14 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
>  	/*
>  	 * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
>  	 * expect success and a truncated value, not #GP.
> +	 *
> +	 * On Hygon CPUs whether or not RDPID is supported in the host, once RDTSCP
> +	 * is supported, MSR_TSC_AUX is able to be accessed.  So, for either RDTSCP
> +	 * or RDPID is supported case and both are supported case, expect
> +	 * success and a truncated value, not #GP.
>  	 */
> -	if (!this_cpu_has(msr->feature) ||
> -	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
> +	if (!is_hygon_msr_tsc_aux_supported(msr) && (!this_cpu_has(msr->feature) ||
> +	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val))) {
>  		u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
>  
>  		__GUEST_ASSERT(vec == GP_VECTOR,
> -- 
> 2.43.0
> 

Re: [PATCH RESEND 2/5] KVM: x86: selftests: Alter the instruction of hypercall on Hygon

[Zhiquan Li]

On 2/10/26 00:37, Sean Christopherson wrote:
> Rather than play a constant game of whack-a-mole and end up with a huge number of
> "host_cpu_is_amd || host_cpu_is_hygon" checks, I would prefer to add (in addition
> to host_cpu_is_hygon) a "host_cpu_is_amd_compatible" flag.
> 
> E.g. slotted in after patch 1, something like this:
> 

Many thanks, Sean!
Let me put these into patch 2, and patch 3 can be dropped.

Best Regards,
Zhiquan

> ---
>  tools/testing/selftests/kvm/include/x86/processor.h  | 1 +
>  tools/testing/selftests/kvm/lib/x86/processor.c      | 8 ++++++--
>  tools/testing/selftests/kvm/x86/fix_hypercall_test.c | 2 +-
>  tools/testing/selftests/kvm/x86/msrs_test.c          | 2 +-
>  tools/testing/selftests/kvm/x86/xapic_state_test.c   | 2 +-
>  5 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/
> testing/selftests/kvm/include/x86/processor.h
> index 1338de7111e7..40e3deb64812 100644
> --- a/tools/testing/selftests/kvm/include/x86/processor.h
> +++ b/tools/testing/selftests/kvm/include/x86/processor.h
> @@ -22,6 +22,7 @@
>  extern bool host_cpu_is_intel;
>  extern bool host_cpu_is_amd;
>  extern bool host_cpu_is_hygon;
> +extern bool host_cpu_is_amd_compatible;
>  extern uint64_t guest_tsc_khz;
>  
>  #ifndef MAX_NR_CPUID_ENTRIES
> diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/
> selftests/kvm/lib/x86/processor.c
> index f6b1c5324931..7b7fd2ad148f 100644
> --- a/tools/testing/selftests/kvm/lib/x86/processor.c
> +++ b/tools/testing/selftests/kvm/lib/x86/processor.c
> @@ -24,6 +24,7 @@ vm_vaddr_t exception_handlers;
>  bool host_cpu_is_amd;
>  bool host_cpu_is_intel;
>  bool host_cpu_is_hygon;
> +bool host_cpu_is_amd_compatible;
>  bool is_forced_emulation_enabled;
>  uint64_t guest_tsc_khz;
>  
> @@ -794,6 +795,7 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus)
>  	sync_global_to_guest(vm, host_cpu_is_intel);
>  	sync_global_to_guest(vm, host_cpu_is_amd);
>  	sync_global_to_guest(vm, host_cpu_is_hygon);
> + sync_global_to_guest(vm, host_cpu_is_amd_compatible);
>  	sync_global_to_guest(vm, is_forced_emulation_enabled);
>  	sync_global_to_guest(vm, pmu_errata_mask);
>  
> @@ -1350,7 +1352,8 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
>  		     "1: vmmcall\n\t"					\
>  		     "2:"						\
>  		     : "=a"(r)						\
> - : [use_vmmcall] "r" (host_cpu_is_amd), inputs); \
> + : [use_vmmcall] "r" (host_cpu_is_amd_compatible), \
> + inputs); \
>  									\
>  	r;								\
>  })
> @@ -1391,7 +1394,7 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm)
>  	max_gfn = (1ULL << (guest_maxphyaddr - vm->page_shift)) - 1;
>  
>  	/* Avoid reserved HyperTransport region on AMD processors.  */
> - if (!host_cpu_is_amd)
> + if (!host_cpu_is_amd_compatible)
>  		return max_gfn;
>  
>  	/* On parts with <40 physical address bits, the area is fully hidden */
> @@ -1427,6 +1430,7 @@ void kvm_selftest_arch_init(void)
>  	host_cpu_is_intel = this_cpu_is_intel();
>  	host_cpu_is_amd = this_cpu_is_amd();
>  	host_cpu_is_hygon = this_cpu_is_hygon();
> + host_cpu_is_amd_compatible = host_cpu_is_amd || host_cpu_is_hygon;
>  	is_forced_emulation_enabled = kvm_is_forced_emulation_enabled();
>  
>  	kvm_init_pmu_errata();
> diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/
> testing/selftests/kvm/x86/fix_hypercall_test.c
> index 762628f7d4ba..00b6e85735dd 100644
> --- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
> +++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
> @@ -52,7 +52,7 @@ static void guest_main(void)
>  	if (host_cpu_is_intel) {
>  		native_hypercall_insn = vmx_vmcall;
>  		other_hypercall_insn  = svm_vmmcall;
> - } else if (host_cpu_is_amd) {
> + } else if (host_cpu_is_amd_compatible) {
>  		native_hypercall_insn = svm_vmmcall;
>  		other_hypercall_insn  = vmx_vmcall;
>  	} else {
> diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/
> selftests/kvm/x86/msrs_test.c
> index 40d918aedce6..4c97444fdefe 100644
> --- a/tools/testing/selftests/kvm/x86/msrs_test.c
> +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
> @@ -81,7 +81,7 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want)
>  	 * is supposed to emulate that behavior based on guest vendor model
>  	 * (which is the same as the host vendor model for this test).
>  	 */
> - if (!host_cpu_is_amd)
> + if (!host_cpu_is_amd_compatible)
>  		return want;
>  
>  	switch (msr) {
> diff --git a/tools/testing/selftests/kvm/x86/xapic_state_test.c b/tools/testing/
> selftests/kvm/x86/xapic_state_test.c
> index 3b4814c55722..0c5e12f5f14e 100644
> --- a/tools/testing/selftests/kvm/x86/xapic_state_test.c
> +++ b/tools/testing/selftests/kvm/x86/xapic_state_test.c
> @@ -248,7 +248,7 @@ int main(int argc, char *argv[])
>  	 * drops writes, AMD does not).  Account for the errata when checking
>  	 * that KVM reads back what was written.
>  	 */
> - x.has_xavic_errata = host_cpu_is_amd &&
> + x.has_xavic_errata = host_cpu_is_amd_compatible &&
>  			     get_kvm_amd_param_bool("avic");
>  
>  	vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC);
> 
> base-commit: 391774310e7309b5a1ee12fac9264e95b1d4a6ee
> --

Re: [PATCH RESEND 4/5] KVM: x86: selftests: Allow the PMU event filter test for Hygon

[Zhiquan Li]

On 2/10/26 00:38, Sean Christopherson wrote:
> Manually handling every check is rather silly, just do:
> 
> diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tools/
> testing/selftests/kvm/x86/pmu_event_filter_test.c
> index 1c5b7611db24..93b61c077991 100644
> --- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
> +++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
> @@ -361,7 +361,8 @@ static bool use_intel_pmu(void)
>   */
>  static bool use_amd_pmu(void)
>  {
> - return host_cpu_is_amd && kvm_cpu_family() >= 0x17;
> + return (host_cpu_is_amd && kvm_cpu_family() >= 0x17) ||
> + host_cpu_is_hygon;
>  }
>  
>  /*

No problem, let me simplify it in V2 patch. Thanks!

Best Regards,
Zhiquan

Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Zhiquan Li]

On 2/10/26 00:41, Sean Christopherson wrote:
> On Mon, Feb 09, 2026, Zhiquan Li wrote:
>> Therefore, the expectation of writing MSR_TSC_AUX reserved bits on Hygon
>> CPUs should be:
>> 1) either RDTSCP or RDPID is supported case, and both are supported
>>    case, expect success and a truncated value, not #GP.
>> 2) neither RDTSCP nor RDPID is supported, expect #GP.
> 
> That's how Intel and AMD behave as well.  I don't understand why there needs to
> be a big pile of special case code for Hygon.  Presumably just fixup_rdmsr_val()
> needs to be changed?
> 

Currently the conditions cannot cover the case that the host *only* supports
RDTSCP but not support RDPID, like Hygon CPU.  Let me give more details for this
test failure.

When testing the case MSR_TEST2(MSR_TSC_AUX, 0x12345678, u64_val, RDPID,
RDTSCP), the cupid bit for RDPID (as feature) of vCPU 0 and vCPU1 will be
removed because host is not supported it, but please note RDTSCP (as feature2)
is supported.  Therefore, the preceding condition “!this_cpu_has(msr->feature)”
here is true and then the test run into the first branch.  Because the feature2
RDTSCP is supported, writing reserved bits (that is, guest_test_reserved_val())
will succeed, unfortunately, the expectation for the first branch is #GP.

The check to fixup_rdmsr_val() is too late, since the preceding condition
already leads to the test run into the wrong branch.

The test can be passed on AMD CPU is because RDPID is usually supported by host,
the cupid bit for RDPID of vCPU 0 and vCPU1 can be kept, then fixup_rdmsr_val()
can drive it to the second branch.  Theoretically, the failure also can be
reproduced on some old AMD CPUs which only support RDTSCP, it’s hard to find
such an old machine to confirm it, but I suppose this case can be covered by
slight changes based on this patch.

Intel CPU no such failure, because writing MSR_TSC_AUX reserved bits results in
#GP is expected behavior.


>>  tools/testing/selftests/kvm/x86/msrs_test.c | 26 +++++++++++++++++----
>>  1 file changed, 21 insertions(+), 5 deletions(-)
>>
>> diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
>> index 40d918aedce6..2f1e800fe691 100644
>> --- a/tools/testing/selftests/kvm/x86/msrs_test.c
>> +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
>> @@ -94,6 +94,17 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want)
>>  	}
>>  }
>>  
>> +/*
>> + * On Hygon processors either RDTSCP or RDPID is supported in the host,
>> + * MSR_TSC_AUX is able to be accessed.
>> + */
>> +static bool is_hygon_msr_tsc_aux_supported(const struct kvm_msr *msr)
>> +{
>> +	return host_cpu_is_hygon &&
>> +			msr->index == MSR_TSC_AUX &&
>> +			(this_cpu_has(msr->feature) || this_cpu_has(msr->feature2));
> 
> Align indentation, but as above, this shouldn't be necessary.
> 

OK, let me fix it if this chunk still needed.

Best Regards,
Zhiquan

>> +}
>> +
>>  static void __rdmsr(u32 msr, u64 want)
>>  {
>>  	u64 val;
>> @@ -174,9 +185,14 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
>>  	/*
>>  	 * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
>>  	 * expect success and a truncated value, not #GP.
>> +	 *
>> +	 * On Hygon CPUs whether or not RDPID is supported in the host, once RDTSCP
>> +	 * is supported, MSR_TSC_AUX is able to be accessed.  So, for either RDTSCP
>> +	 * or RDPID is supported case and both are supported case, expect
>> +	 * success and a truncated value, not #GP.
>>  	 */
>> -	if (!this_cpu_has(msr->feature) ||
>> -	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
>> +	if (!is_hygon_msr_tsc_aux_supported(msr) && (!this_cpu_has(msr->feature) ||
>> +	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val))) {
>>  		u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
>>  
>>  		__GUEST_ASSERT(vec == GP_VECTOR,
>> -- 
>> 2.43.0
>>

Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Sean Christopherson]

On Tue, Feb 10, 2026, Zhiquan Li wrote:
> 
> On 2/10/26 00:41, Sean Christopherson wrote:
> > On Mon, Feb 09, 2026, Zhiquan Li wrote:
> >> Therefore, the expectation of writing MSR_TSC_AUX reserved bits on Hygon
> >> CPUs should be:
> >> 1) either RDTSCP or RDPID is supported case, and both are supported
> >>    case, expect success and a truncated value, not #GP.
> >> 2) neither RDTSCP nor RDPID is supported, expect #GP.
> > 
> > That's how Intel and AMD behave as well.  I don't understand why there needs to
> > be a big pile of special case code for Hygon.  Presumably just fixup_rdmsr_val()
> > needs to be changed?
> > 
> 
> Currently the conditions cannot cover the case that the host *only* supports
> RDTSCP but not support RDPID, like Hygon CPU.  Let me give more details for this
> test failure.
> 
> When testing the case MSR_TEST2(MSR_TSC_AUX, 0x12345678, u64_val, RDPID,
> RDTSCP), the cupid bit for RDPID (as feature) of vCPU 0 and vCPU1 will be
> removed because host is not supported it, but please note RDTSCP (as feature2)
> is supported.  Therefore, the preceding condition “!this_cpu_has(msr->feature)”
> here is true and then the test run into the first branch.  Because the feature2
> RDTSCP is supported, writing reserved bits (that is, guest_test_reserved_val())
> will succeed, unfortunately, the expectation for the first branch is #GP.
> 
> The check to fixup_rdmsr_val() is too late, since the preceding condition
> already leads to the test run into the wrong branch.
> 
> The test can be passed on AMD CPU is because RDPID is usually supported by host,
> the cupid bit for RDPID of vCPU 0 and vCPU1 can be kept, then fixup_rdmsr_val()
> can drive it to the second branch.  Theoretically, the failure also can be
> reproduced on some old AMD CPUs which only support RDTSCP, it’s hard to find
> such an old machine to confirm it, but I suppose this case can be covered by
> slight changes based on this patch.
> 
> Intel CPU no such failure, because writing MSR_TSC_AUX reserved bits results in
> #GP is expected behavior.

Gah, I think I tested -rdpid and -rdtscp in a VM on Intel, but not AMD.  I think
the fix is just this:

diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
index 40d918aedce6..ebd900e713c1 100644
--- a/tools/testing/selftests/kvm/x86/msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/msrs_test.c
@@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
         * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
         * expect success and a truncated value, not #GP.
         */
-       if (!this_cpu_has(msr->feature) ||
+       if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) ||
            msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
                u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);

Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Zhiquan Li]

On 2/11/26 04:02, Sean Christopherson wrote:
> Gah, I think I tested -rdpid and -rdtscp in a VM on Intel, but not AMD.  I think
> the fix is just this:
> 
> diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/
> selftests/kvm/x86/msrs_test.c
> index 40d918aedce6..ebd900e713c1 100644
> --- a/tools/testing/selftests/kvm/x86/msrs_test.c
> +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
> @@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
>          * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
>          * expect success and a truncated value, not #GP.
>          */
> - if (!this_cpu_has(msr->feature) ||
> + if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) ||
>             msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
>                 u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);

Perfect!  You found the root cause and fixed it.
I’ve verified the fix on Hygon platform, I will test it on Intel and AMD
platforms as well to make sure there is no regression.
I’m going to include the you fix in the V2 series.  Since my modifications are
totally miss the point, I will remove my SoB and only add my “Reported-by:” tag,
I suppose the SoB position would be wait for you, Sean :-)

Great many thanks for your help for the whole series!!

Best Regards,
Zhiquan

Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Sean Christopherson]

On Wed, Feb 11, 2026, Zhiquan Li wrote:
> 
> On 2/11/26 04:02, Sean Christopherson wrote:
> > Gah, I think I tested -rdpid and -rdtscp in a VM on Intel, but not AMD.  I think
> > the fix is just this:
> > 
> > diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/
> > selftests/kvm/x86/msrs_test.c
> > index 40d918aedce6..ebd900e713c1 100644
> > --- a/tools/testing/selftests/kvm/x86/msrs_test.c
> > +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
> > @@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
> >          * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
> >          * expect success and a truncated value, not #GP.
> >          */
> > - if (!this_cpu_has(msr->feature) ||
> > + if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) ||
> >             msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
> >                 u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
> 
> Perfect!  You found the root cause and fixed it.
> I’ve verified the fix on Hygon platform, I will test it on Intel and AMD
> platforms as well to make sure there is no regression.
> I’m going to include the you fix in the V2 series.  Since my modifications are
> totally miss the point, I will remove my SoB and only add my “Reported-by:” tag,
> I suppose the SoB position would be wait for you, Sean :-)

Nice!  Here's a full patch for v2.

--
From: Sean Christopherson <seanjc@google.com>
Date: Wed, 11 Feb 2026 08:18:47 -0800
Subject: [PATCH] KVM: selftests: Fix reserved value WRMSR testcase for
 multi-feature MSRs

When determining whether or not a WRMSR with reserved bits will #GP or
succeed due to the WRMSR not existing per the guest virtual CPU model,
expect failure if and only if _all_ features associated with the MSR are
unsupported.  Checking only the primary feature results in false failures
when running on AMD and Hygon CPUs with only one of RDPID or RDTSCP, as
AMD/Hygon CPUs ignore MSR_TSC_AUX[63:32], i.e. don't treat the bits as
reserved, and so #GP only if the MSR is unsupported.

Fixes: 9c38ddb3df94 ("KVM: selftests: Add an MSR test to exercise guest/host and read/write")
Reported-by: Zhiquan Li <zhiquan_li@163.com>
Closes: https://lore.kernel.org/all/20260209041305.64906-6-zhiquan_li@163.com
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 tools/testing/selftests/kvm/x86/msrs_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
index 40d918aedce6..ebd900e713c1 100644
--- a/tools/testing/selftests/kvm/x86/msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/msrs_test.c
@@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
 	 * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
 	 * expect success and a truncated value, not #GP.
 	 */
-	if (!this_cpu_has(msr->feature) ||
+	if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) ||
 	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
 		u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
 

base-commit: e944fe2c09f405a2e2d147145c9b470084bc4c9a
--