From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92FB6381710 for ; Mon, 9 Feb 2026 16:41:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770655265; cv=none; b=lba3AA7HCPrPqEK4PD8uRK/bfzxcxXDNBc3CN/b+zkSzAju8uiWbFFJm098/KHOsoJGA8s7PCnIbI3uZFXrsV28HtdL+Oo/bAtunoiQhWjDEB5+YbUypo93mNY5Oa2F4nisA9VNgV2X64IWys/xfo5DKQT0qo4ythO3WyGnbQA0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770655265; c=relaxed/simple; bh=yorrzb7NRKtIXt5G2GDhvZgIgQxURMT3QqjSzo+rUa8=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=N0JcIJtaxTB82fwtidzyqV/SYvs5yGPB7khZU0snUGlW4e1GQR6L4woZWHfE8qcDKufaW751IG83P7BPRHObz0nU4fKa7UyI/9A+C4zgihZAETtgQkpTUNtdQOtL64F5FI0nacEnux/4udryvTGE8q7GUmc23XRx1eiBngzLkoM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=2p3l6JnD; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="2p3l6JnD" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-2a7b7f04a11so139882825ad.3 for ; Mon, 09 Feb 2026 08:41:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1770655265; x=1771260065; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=EKHOCX1WV2Qxb28cI5D8Ij6jh1+CDP36MN7+6L6pt98=; b=2p3l6JnDt56LkZGCfUzhncyRD67KNPvH8+2+z5hOTHYhlL7DGG8u8AII5DSDSZe+XO +u99eQb5srdKaNMEA+zcUBrsnz7ZqsrNVr5xnrBVEo4hsoAYQB3zPDqYvJ0cS8Hejhxb h9mGBih0cUN1/q76orbH8zMTUzzOb5grFppo3PABnSae5Kj/UHacO1fguUmdERo9GU4f oojaaFfOWRlbXToCvXFcshzNtnKvuIu6vUzyRf71intI/dYWLhhioJrUUxzYE2M/6tIc 9aDTwiw/VFGyg3z205bUkQZX7Ooo9kHr0qQnqWUNeBaIhWqFSdSw0R4twqfuOnnq0Z9Z +iwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770655265; x=1771260065; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EKHOCX1WV2Qxb28cI5D8Ij6jh1+CDP36MN7+6L6pt98=; b=n2NB2FDizCjNUwsVd4qsOdLYhkx0cGY0nxQGbN86hBGLrhizXdSZCg3wbTtPaqo0Td dAZV3mjh8ov4pHY1/IXsle3/81/PhRQXRdE/5wH32uaT8g0cyOnGxhdyt//z0JTZWw7L N4Fkg/V0+kpty7K2c4azg/OWbCcDrkDJd/2GS1371ejJxIVw86nF9bSQWvQV6veyMLy6 qW+kynesK8+p0nOn0LeeiLy/O4znEv6D8vd5M+trNhbq+gCQ9gWPd4TZ/r7N0vXQdXN7 sbTtb7vKQc34bmhPCJApMOx+YbAjlKZw8LDrXu+mD7sPrroXPKrzImwY8TOc8kLVJXSU Zs+A== X-Forwarded-Encrypted: i=1; AJvYcCUvqv2HaKMrMwuMAeHKCDou5gcobiqJnvVl6Q6WZdjJhpqQx3edItecoNA0MAA7FCaXCgA11npjFyX1AM8=@vger.kernel.org X-Gm-Message-State: AOJu0Yx2Fu0gGOxMQ6/uU9MnF+GxwwfRMOkKXdT34ufOlRcMiPkXd4jS 3Gze1baV0Cp10LmBjzYNMEKHfyBNHBxrw3I6SOTN5Fk8IepOcSaVYPnfS6MBs0otc1eKlYztaLP LLGA/yQ== X-Received: from plas9.prod.google.com ([2002:a17:903:2009:b0:2aa:d604:fb13]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:1a24:b0:2a9:6281:6a48 with SMTP id d9443c01a7336-2a962816e6dmr93478985ad.44.1770655264923; Mon, 09 Feb 2026 08:41:04 -0800 (PST) Date: Mon, 9 Feb 2026 08:41:03 -0800 In-Reply-To: <20260209041305.64906-6-zhiquan_li@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260209041305.64906-1-zhiquan_li@163.com> <20260209041305.64906-6-zhiquan_li@163.com> Message-ID: Subject: Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon From: Sean Christopherson To: Zhiquan Li Cc: pbonzini@redhat.com, shuah@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Mon, Feb 09, 2026, Zhiquan Li wrote: > Therefore, the expectation of writing MSR_TSC_AUX reserved bits on Hygon > CPUs should be: > 1) either RDTSCP or RDPID is supported case, and both are supported > case, expect success and a truncated value, not #GP. > 2) neither RDTSCP nor RDPID is supported, expect #GP. That's how Intel and AMD behave as well. I don't understand why there needs to be a big pile of special case code for Hygon. Presumably just fixup_rdmsr_val() needs to be changed? > Signed-off-by: Zhiquan Li > --- > tools/testing/selftests/kvm/x86/msrs_test.c | 26 +++++++++++++++++---- > 1 file changed, 21 insertions(+), 5 deletions(-) > > diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c > index 40d918aedce6..2f1e800fe691 100644 > --- a/tools/testing/selftests/kvm/x86/msrs_test.c > +++ b/tools/testing/selftests/kvm/x86/msrs_test.c > @@ -77,11 +77,11 @@ static bool ignore_unsupported_msrs; > static u64 fixup_rdmsr_val(u32 msr, u64 want) > { > /* > - * AMD CPUs drop bits 63:32 on some MSRs that Intel CPUs support. KVM > - * is supposed to emulate that behavior based on guest vendor model > + * AMD and Hygon CPUs drop bits 63:32 on some MSRs that Intel CPUs support. > + * KVM is supposed to emulate that behavior based on guest vendor model > * (which is the same as the host vendor model for this test). > */ > - if (!host_cpu_is_amd) > + if (!host_cpu_is_amd && !host_cpu_is_hygon) > return want; > > switch (msr) { > @@ -94,6 +94,17 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want) > } > } > > +/* > + * On Hygon processors either RDTSCP or RDPID is supported in the host, > + * MSR_TSC_AUX is able to be accessed. > + */ > +static bool is_hygon_msr_tsc_aux_supported(const struct kvm_msr *msr) > +{ > + return host_cpu_is_hygon && > + msr->index == MSR_TSC_AUX && > + (this_cpu_has(msr->feature) || this_cpu_has(msr->feature2)); Align indentation, but as above, this shouldn't be necessary. > +} > + > static void __rdmsr(u32 msr, u64 want) > { > u64 val; > @@ -174,9 +185,14 @@ void guest_test_reserved_val(const struct kvm_msr *msr) > /* > * If the CPU will truncate the written value (e.g. SYSENTER on AMD), > * expect success and a truncated value, not #GP. > + * > + * On Hygon CPUs whether or not RDPID is supported in the host, once RDTSCP > + * is supported, MSR_TSC_AUX is able to be accessed. So, for either RDTSCP > + * or RDPID is supported case and both are supported case, expect > + * success and a truncated value, not #GP. > */ > - if (!this_cpu_has(msr->feature) || > - msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) { > + if (!is_hygon_msr_tsc_aux_supported(msr) && (!this_cpu_has(msr->feature) || > + msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val))) { > u8 vec = wrmsr_safe(msr->index, msr->rsvd_val); > > __GUEST_ASSERT(vec == GP_VECTOR, > -- > 2.43.0 >