From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 141A0168BD for ; Tue, 10 Feb 2026 16:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770741016; cv=none; b=ZOgOP63vmovHk0i33ExY8gAMVdSSfMY6crX49875tdVVsercmuKQxwRnIwHwwjIwYZNDJcA9zgPC1/Lw3MMQNe3TG33mrv8GCAePmOPW5lRWnnfd1rV5z3ocU6T43QfmOdPDaMWbtgns4+bF7a29z1p/qE72fo3bsMF4W80iFsk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770741016; c=relaxed/simple; bh=apf+WxV7DF9xXs7mg57Z4stowwqhdNdVzUotm2+M5fM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=gCLH44bEIAIRuWUW0vUCP0CWE76rStk+G9rcNQ5Yw19fmVCAqIW6XicVrozLuE7EbUVHr8wFG0yEfcL+Ms6/Vl9Rsqszg6pViHDNgoLfwxbjcwsb3MQoVJoWdm1NeOi73C/ZUKsAphcpuFd+JHgxH2ScNRQTzlzMBH5CyjTx528= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=dDBNiYK3; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="dDBNiYK3" Date: Tue, 10 Feb 2026 08:29:58 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1770741012; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=ciUjhVvToHNuGHTWYUtNytWkQjP8xnn0ronWwShe/v4=; b=dDBNiYK3kAcBNyjmK6tAsif/GJhG5jdJ6YP36U3pdsspXExzOFwt0xJmk971+m1noj6eBs QZcarLuLNpMR2MvCWsG+jNIfEbgwuGDnS3piJxgnie6cUiXA6SytzhmUoZ+V00noIJdLz+ sGQN6ankIQEd6jfvWZverOQFyGwElss= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Shakeel Butt To: Dev Jain Cc: Harry Yoo , Andrew Morton , Johannes Weiner , Michal Hocko , Roman Gushchin , Muchun Song , Qi Zheng , Vlastimil Babka , linux-mm@kvack.org, cgroups@vger.kernel.org, linux-kernel@vger.kernel.org, Meta kernel team Subject: Re: [PATCH 1/4] memcg: use mod_node_page_state to update stats Message-ID: References: <1052a452-9ba3-4da7-be47-7d27d27b3d1d@arm.com> <2638bd96-d8cc-4733-a4ce-efdf8f223183@arm.com> <51819ca5a15d8928caac720426cd1ce82e89b429@linux.dev> <05aec69b-8e73-49ac-aa89-47b371fb6269@arm.com> <4847c300-c7bb-4259-867c-4bbf4d760576@arm.com> <7df681ae0f8254f09de0b8e258b909eaacafadf4@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT On Tue, Feb 10, 2026 at 01:08:49PM +0530, Dev Jain wrote: [...] > > >> > > Oh so it is arm64 specific issue. I tested on x86-64 machine and it solves > > the little regression it had before. So, on arm64 all this_cpu_ops i.e. without > > double underscore, uses LL/SC instructions. > > > > Need more thought on this. > > > >>> Also can you confirm whether my analysis of the regression was correct? > >>> Because if it was, then this diff looks wrong - AFAIU preempt_disable() > >>> won't stop an irq handler from interrupting the execution, so this > >>> will introduce a bug for code paths running in irq context. > >>> > >> I was worried about the correctness too, but this_cpu_add() is safe > >> against IRQs and so the stat will be _eventually_ consistent? > >> > >> Ofc it's so confusing! Maybe I'm the one confused. > > Yeah there is no issue with proposed patch as it is making the function > > re-entrant safe. > > Ah yes, this_cpu_add() does the addition in one shot without read-modify-write. > > I am still puzzled whether the original patch was a bug fix or an optimization. The original patch was a cleanup patch. The memcg stats update functions were already irq/nmi safe without disabling irqs and that patch did the same for the numa stats. Though it seems like that is causing regression for arm64 as this_cpu* ops are expensive on arm64. > The patch description says that node stat updation uses irq unsafe interface. > Therefore, we had foo() calling __foo() nested with local_irq_save/restore. But > there were code paths which directly called __foo() - so, your patch fixes a bug right No, those places were already disabling irqs and should be fine. I am working on adding batched stats update functionality in the hope that will fix the regression. >