From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60815C145; Wed, 11 Feb 2026 00:40:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770770426; cv=none; b=Np7YR5+Mb2J+RABpYSi8h6EPybGFTTu82ZTBiXnsSeC3pWkub1vfGN6oAu3pcXm3uKP7+OfFW5KMZPtVEg1cfxWMo6UkB0f8VdVOf4hszK8rffJ0WIEV5EwvVPbnj59GadwHS+uUt6r1DXG2R+1gBKupjbiFy8m1kCMitdUZA9A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770770426; c=relaxed/simple; bh=YDyBWPm08onVp7slxg+PyGMsPp1MAexWPC++OxPk4+M=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=u45QHoDOTX+T9WdQkEd269oTYthsxCWqSefkHVjFYsjpp3/ovJdWnJS+xKVvKSMm338HpZ9UaM2mJ7GC+NMmawA2Fy1LcO14AW1ebtZv7T7votIUGbF2pcK/eE+QoL+YTexHGfV57lOz6gs2yhK6IL1epIo6zZaSGWr/knzrr54= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZJ120l/z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZJ120l/z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51C05C116C6; Wed, 11 Feb 2026 00:40:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770770426; bh=YDyBWPm08onVp7slxg+PyGMsPp1MAexWPC++OxPk4+M=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ZJ120l/znObnboowjFJ5TRY7Uyua+I5gmOMjaZeqvH6bmV4CUndoxNcDAzoDgqj2H p94ccgkPgE1097G/y73+DqD92MeOGEj7wZ1F1TTxKd7F83SPCgttt5Q3/c9j5WjPa/ 8v23pgaXcN4rjzDWbj2fjX3p1X7BCvv4ynaih8eLDmyFGDxHzTtk4SJ1S1LkPAbZVV 6DddDinC8Xft5o8qjB3eiVTgzXOZhV48/0AtsVi1+19Jo8ac6hHtROLT7f962nRr8e DuTBrrK2SMlC323VsuYNrE/xhJ8C/8dyI2bY92/dTf3MTv3Tyxo8+0gqleHAt4JaQq OZqieV3Np75cg== Date: Tue, 10 Feb 2026 16:40:23 -0800 From: Drew Fustini To: Reinette Chatre Cc: "Luck, Tony" , Babu Moger , James Morse , Dave Martin , Ben Horgan , corbet@lwn.net, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, juri.lelli@redhat.com, vincent.guittot@linaro.org, dietmar.eggemann@arm.com, rostedt@goodmis.org, bsegall@google.com, mgorman@suse.de, vschneid@redhat.com, akpm@linux-foundation.org, pawan.kumar.gupta@linux.intel.com, pmladek@suse.com, feng.tang@linux.alibaba.com, kees@kernel.org, arnd@arndb.de, fvdl@google.com, lirongqing@baidu.com, bhelgaas@google.com, seanjc@google.com, xin@zytor.com, manali.shukla@amd.com, dapeng1.mi@linux.intel.com, chang.seok.bae@intel.com, mario.limonciello@amd.com, naveen@kernel.org, elena.reshetova@intel.com, thomas.lendacky@amd.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, peternewman@google.com, eranian@google.com, gautham.shenoy@amd.com Subject: Re: [RFC PATCH 00/19] x86,fs/resctrl: Support for Global Bandwidth Enforcement and Priviledge Level Zero Association Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Feb 09, 2026 at 04:27:47PM -0800, Reinette Chatre wrote: > Adding Ben > > On 2/3/26 11:58 AM, Luck, Tony wrote: > > On Wed, Jan 21, 2026 at 03:12:38PM -0600, Babu Moger wrote: > >> Privilege Level Zero Association (PLZA) > >> > >> Privilege Level Zero Association (PLZA) allows the hardware to > >> automatically associate execution in Privilege Level Zero (CPL=0) with a > >> specific COS (Class of Service) and/or RMID (Resource Monitoring > >> Identifier). The QoS feature set already has a mechanism to associate > >> execution on each logical processor with an RMID or COS. PLZA allows the > >> system to override this per-thread association for a thread that is > >> executing with CPL=0. > > > > Adding Drew, and prodding Dave & James, for this discussion. > > > > At LPC it was stated that both ARM and RISC-V already have support > > to run kernel code with different quality of service parameters from > > user code. Sorry, for RISC-V, I should clarify that there is no hardware feature that changes the QoS identifier value when switching between kernel mode and user mode. This could be done in the kernel task switching code, but there is no implicit hardware operation. Thanks, Drew