Re: [PATCH v2 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices

[Nicolin Chen <nicolinc@nvidia.com>]

On Tue, Feb 24, 2026 at 11:55:34AM +0000, Jonathan Cameron wrote:
> On Mon, 23 Feb 2026 14:52:20 -0800
> Nicolin Chen <nicolinc@nvidia.com> wrote:
> > +/*
> > + * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on
> > + * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host
> > + * by means of an ATS request on CXL.io.
> > + *
> > + * In other world, CXL.cache devices cannot access physical memory without ATS.
> 
> Maybe tweak that to "host physical memory"
> 
> There are too many physical memories in CXL land...
> 
> > + */
> > +static bool pci_cxl_ats_always_on(struct pci_dev *pdev)
> > +{
> > +	int offset;
> > +	u16 cap;
> > +
> > +	offset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
> > +					   PCI_DVSEC_CXL_DEVICE);
> > +	if (!offset)
> > +		return false;
> > +
> > +	pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap);
> > +	if (cap & PCI_DVSEC_CXL_CACHE_CAPABLE)
> > +		return true;
> 
> Could just do
> 
> 	return cap & PCI_DVSEC_CXL_CACHE_CAPABLE;
> 
> Unless the thinking is there may be other stuff that comes here.

I will fix both. Thanks for the review!

Nicolin