From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 548043DA7F5; Wed, 25 Feb 2026 15:51:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772034663; cv=none; b=T7Zx7ErIAwzoXvdawWpje6LSH9V66yMWVr0QGuIHgucgkGTEOO8t33HqBBKpIqErk8ShRyzW3tGnKrVwSfQxxH3i/hwzp/w+R3p65Gmm7tA3iqY06H+Ip3cz8O1SN3iSuLcI0H8MJ3XObwHDACeebXUBiJXVE2the0lzBwxja6A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772034663; c=relaxed/simple; bh=X8g+EKJL0vZnYgJbnZJBCkMj0KCIXHLnrvIicphTvcg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=MR4skSslCM8NWDMgKjskkSzEpSF/4wIrcNjSarYWhbr7bMg/FealIu4DfqczkolK+LaBQ355vQMf8Qh065ltt7A6JQN0GU0YjkFVdMsZGfMbk1pkUerxL3kzgr/rfDg23PiVh8eEFT6vZjlLY8LCUPyMFCT8zMljRy83bnaRoVM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N8o8c6fx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N8o8c6fx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 187F0C116D0; Wed, 25 Feb 2026 15:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772034663; bh=X8g+EKJL0vZnYgJbnZJBCkMj0KCIXHLnrvIicphTvcg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=N8o8c6fx7S2iXqLGrOBHQYvcEjWQG5022FEv9UcaDkP34xHM0E5ber/YhVZZJ7TDJ CmonH3kI+u7XPVDT6HakxUNk6XaTfLiUErrtz15xA+amKw+aR7DLJxX5crqo3Vj23y ha8ymHj5xiUMc7OdnyEepYVJrN8Xo9CXha27eWqxeexBZWgLI8h5Se7XX6MsM3qOYC PueqjmhMJa59WDVNHonUx88k63SjrdKBN71BGuIPR/BImGSF37PiacUkuArAzcg6zs 7txFnlhhrz7LlIGf8EGIHyQZ/UYqfI6d9lioag4Y/n6KbkRjxo5SIKImiSdoeutd6u yWRrawVpZN9Sw== Date: Wed, 25 Feb 2026 17:50:45 +0200 From: Mike Rapoport To: Jinjie Ruan Cc: corbet@lwn.net, skhan@linuxfoundation.org, catalin.marinas@arm.com, will@kernel.org, chenhuacai@kernel.org, kernel@xen0n.name, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, chleroy@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, akpm@linux-foundation.org, bhe@redhat.com, vgoyal@redhat.com, dyoung@redhat.com, rdunlap@infradead.org, pmladek@suse.com, dapeng1.mi@linux.intel.com, kees@kernel.org, paulmck@kernel.org, lirongqing@baidu.com, arnd@arndb.de, ardb@kernel.org, leitao@debian.org, cfsworks@gmail.com, ryan.roberts@arm.com, sourabhjain@linux.ibm.com, tangyouling@kylinos.cn, eajames@linux.ibm.com, hbathini@linux.ibm.com, ritesh.list@gmail.com, songshuaishuai@tinylab.org, samuel.holland@sifive.com, kevin.brodsky@arm.com, vishal.moola@gmail.com, junhui.liu@pigmoral.tech, coxu@redhat.com, liaoyuanhong@vivo.com, fuqiang.wang@easystack.cn, jbohac@suse.cz, brgerst@gmail.com, x86@kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, kexec@lists.infradead.org Subject: Re: [PATCH v6 0/5] arm64/riscv: Add support for crashkernel CMA reservation Message-ID: References: <20260224085342.387996-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260224085342.387996-1-ruanjinjie@huawei.com> On Tue, Feb 24, 2026 at 04:53:37PM +0800, Jinjie Ruan wrote: > The crash memory allocation, and the exclude of crashk_res, crashk_low_res > and crashk_cma memory are almost identical across different architectures, > This patch set handle them in crash core in a general way, which eliminate > a lot of duplication code. > > And add support for crashkernel CMA reservation for arm64 and riscv. > > Rebased on v7.0-rc1. > > Basic test were performed on QEMU platforms for x86, ARM64, and RISC-V > architectures with the following parameters: > > "cma=256M crashkernel=256M crashkernel=64M,cma" > > Changes in v6: > - Update the crash core exclude code as Mike suggested. > - Rebased on v7.0-rc1. > - Add acked-by. > - Link to v5: https://lore.kernel.org/all/20260212101001.343158-1-ruanjinjie@huawei.com/ > > Changes in v5: > - Fix the kernel test robot build warnings. > - Sort crash memory ranges before preparing elfcorehdr for powerpc > - Link to v4: https://lore.kernel.org/all/20260209095931.2813152-1-ruanjinjie@huawei.com/ > > Changes in v4: > - Move the size calculation (and the realloc if needed) into the > generic crash. > - Link to v3: https://lore.kernel.org/all/20260204093728.1447527-1-ruanjinjie@huawei.com/ > > Changs in v3: > - Exclude crash kernel memory in crash core as Mike suggested. > - Add acked-by. > > Jinjie Ruan (4): > crash: Exclude crash kernel memory in crash core > crash: Use crash_exclude_core_ranges() on powerpc > arm64: kexec: Add support for crashkernel CMA reservation > riscv: kexec: Add support for crashkernel CMA reservation > > Sourabh Jain (1): > powerpc/crash: sort crash memory ranges before preparing elfcorehdr Overall LGTM, I had a comment about arm64 and riscv patches, but other than that Acked-by: Mike Rapoport (Microsoft) -- Sincerely yours, Mike.