Re: [PATCH 1/4] PCI: endpoint: Add reserved region type for MSI-X Table and PBA

[Niklas Cassel <cassel@kernel.org>]

On Mon, Feb 23, 2026 at 01:04:53AM +0530, Manikanta Maddireddy wrote:
> Add PCI_EPC_BAR_RSVD_MSIX_CTRL_MMIO to enum pci_epc_bar_rsvd_region_type
> so that endpoint controllers can describe hardware-owned MSI-X Table and
> PBA (Pending Bit Array) regions behind a BAR_RESERVED BAR.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  include/linux/pci-epc.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index c181c6d107b7..89ab7d07c5d6 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -214,6 +214,7 @@ enum pci_epc_bar_type {
>  /**
>   * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
>   * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
> + * @PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM: MSI-X table and PBA structures

Is it perhaps better to have MSI-X table and PBA structure as two separate
entries?

E.g. in RK3588 TRM:

BAR4: MSI-X Table
Offset: 0x4000
MSI-X Table

BAR4: MSI-X PBA
Offset: 0x5000
MSI-X PBA

Because, at least on RK3588, these seem to have two separate fixed offsets.

Yes, you can probably read PCI_MSIX_TABLE_SIZE in the MSI-X capability.

But, AFAICT from reading the RK3588 TRM (regardless of the size of the
MSI-X table), the PBA is always at offset 0x5000.


Kind regards,
Niklas


>   *
>   * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
>   * reprogrammed by EPF drivers. Some of them still expose fixed subregions that
> @@ -221,6 +222,7 @@ enum pci_epc_bar_type {
>   */
>  enum pci_epc_bar_rsvd_region_type {
>  	PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
> +	PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM,
>  };
>  
>  /**
> -- 
> 2.34.1
>