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From: Niklas Cassel <cassel@kernel.org>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,
	thierry.reding@gmail.com, jonathanh@nvidia.com,
	kishon@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org,
	Frank.Li@nxp.com, den@valinux.co.jp, hongxing.zhu@nxp.com,
	jingoohan1@gmail.com, vidyas@nvidia.com, 18255117159@163.com,
	linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit
Date: Wed, 25 Feb 2026 18:31:31 +0100	[thread overview]
Message-ID: <aZ8x80iu6p7XBD2W@ryzen> (raw)
In-Reply-To: <20260222193456.2460963-3-mmaddireddy@nvidia.com>

On Mon, Feb 23, 2026 at 01:04:54AM +0530, Manikanta Maddireddy wrote:
> BAR0 is capable of supporting various sizes via DBI2 BAR registers
> programmed in dw_pcie_ep_set_bar_programmable(). Remove the 1MB fixed
> size from pci_epc_features and set the BAR type to BAR_PROGRAMMABLE.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4a3b50322204..3c84a230dc79 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2000,11 +2000,11 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  	return 0;
>  }
>  
> +/* Tegra EP: BAR0 = 64-bit programmable BAR */
>  static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.linkup_notifier = true,
>  	.msi_capable = true,
> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
> -			.only_64bit = true, },
> +	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },

If BAR_PROGRAMMABLE, you don't strictly need .type at all, as
BAR_PROGRAMMABLE is (and has always been) the default, defined as value 0.
(So you could simply drop .type from the initializer.)



Are you sure that the BAR is Programmable and not Resizable though?
Because historically, a lot of BARs were defined as Fixed size BARs with
size 1 MB, because there was no Resizable BAR support yet
(the minimum size of a Resizable BAR is 1 MB).

See e.g.:
6a6b66f7e607 ("PCI: keystone: Describe Resizable BARs as Resizable BARs")
aba2b17810d7 ("PCI: dw-rockchip: Describe Resizable BARs as Resizable BARs")


One easy way to check this is to just do (on the host side):

# lspci -s 0000:01:00.0  -vvv | grep Resizable
        Capabilities: [2e8 v1] Physical Resizable BAR

Here you see e.g. that RK3588 based EP implements the "Physical Resizable BAR"
capability.
(Replace 0000:01:00.0 with the BDF of your Tegra based EP.)


Kind regards,
Niklas

  reply	other threads:[~2026-02-25 17:31 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-22 19:34 [PATCH 0/4] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support Manikanta Maddireddy
2026-02-22 19:34 ` [PATCH 1/4] PCI: endpoint: Add reserved region type for MSI-X Table and PBA Manikanta Maddireddy
2026-02-25 17:21   ` Niklas Cassel
2026-02-22 19:34 ` [PATCH 2/4] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit Manikanta Maddireddy
2026-02-25 17:31   ` Niklas Cassel [this message]
2026-03-03  7:19     ` Manikanta Maddireddy
2026-02-22 19:34 ` [PATCH 3/4] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED Manikanta Maddireddy
2026-02-25 17:51   ` Niklas Cassel
2026-02-22 19:34 ` [PATCH 4/4] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries Manikanta Maddireddy
2026-02-25 17:58   ` Niklas Cassel
2026-02-25 18:16     ` Niklas Cassel

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