[PATCH 0/4] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support

[PATCH 0/4] PCI: endpoint: Add Tegra194/234 BAR layout and pci_endpoint_test support

[Manikanta Maddireddy]

This series is on top of https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u

This series wires up Tegra194 and Tegra234 PCI endpoint controllers to the
shared PCI endpoint and test infrastructure:

1. Add a new reserved-region type for MSI-X (Table and PBA) so EPC drivers
   can describe hardware-owned MSI-X regions behind a BAR_RESERVED BAR.

2. Make Tegra194 BAR0 programmable and drop the 1MB fixed size so EPF
   drivers can use it with arbitrary sizes via the existing DBI2 BAR
   programmable path.

3. Expose Tegra194 BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED with
   the appropriate reserved subregions (MSI-X 128KB, DMA 4KB), keeping
   CONSECUTIVE_BAR_TEST working while allowing the host to use these BARs.

4. Add Tegra194 and Tegra234 to the pci_endpoint_test device table so the
   endpoint test driver can bind and run on these controllers.

Tested with pci_endpoint_test on Tegra194/Tegra234 endpoint.

./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma
TAP version 13
1..13
# Starting 13 tests from 8 test cases.
#  RUN           pci_ep_bar.BAR0.BAR_TEST ...
#            OK  pci_ep_bar.BAR0.BAR_TEST
ok 1 pci_ep_bar.BAR0.BAR_TEST
#  RUN           pci_ep_bar.BAR1.BAR_TEST ...
#      SKIP      BAR is disabled
#            OK  pci_ep_bar.BAR1.BAR_TEST
ok 2 pci_ep_bar.BAR1.BAR_TEST # SKIP BAR is disabled
#  RUN           pci_ep_bar.BAR2.BAR_TEST ...
#      SKIP      BAR is reserved
#            OK  pci_ep_bar.BAR2.BAR_TEST
ok 3 pci_ep_bar.BAR2.BAR_TEST # SKIP BAR is reserved
#  RUN           pci_ep_bar.BAR3.BAR_TEST ...
#      SKIP      BAR is disabled
#            OK  pci_ep_bar.BAR3.BAR_TEST
ok 4 pci_ep_bar.BAR3.BAR_TEST # SKIP BAR is disabled
#  RUN           pci_ep_bar.BAR4.BAR_TEST ...
#      SKIP      BAR is reserved
#            OK  pci_ep_bar.BAR4.BAR_TEST
ok 5 pci_ep_bar.BAR4.BAR_TEST # SKIP BAR is reserved
#  RUN           pci_ep_bar.BAR5.BAR_TEST ...
#      SKIP      BAR is disabled
#            OK  pci_ep_bar.BAR5.BAR_TEST
ok 6 pci_ep_bar.BAR5.BAR_TEST # SKIP BAR is disabled
#  RUN           pci_ep_basic.CONSECUTIVE_BAR_TEST ...
#            OK  pci_ep_basic.CONSECUTIVE_BAR_TEST
ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST
#  RUN           pci_ep_basic.LEGACY_IRQ_TEST ...
#            OK  pci_ep_basic.LEGACY_IRQ_TEST
ok 8 pci_ep_basic.LEGACY_IRQ_TEST
#  RUN           pci_ep_basic.MSI_TEST ...
#      SKIP      MSI17 is disabled
#            OK  pci_ep_basic.MSI_TEST
ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled
#  RUN           pci_ep_basic.MSIX_TEST ...
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X1
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X2
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X3
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X4
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X5
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X6
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X7
# pci_endpoint_test.c:146:MSIX_TEST:Expected 0 (0) == ret (-5)
# pci_endpoint_test.c:146:MSIX_TEST:Test failed for MSI-X8
#      SKIP      MSI-X9 is disabled
#            OK  pci_ep_basic.MSIX_TEST
ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled
#  RUN           pci_ep_data_transfer.memcpy.READ_TEST ...
#            OK  pci_ep_data_transfer.memcpy.READ_TEST
ok 11 pci_ep_data_transfer.memcpy.READ_TEST
#  RUN           pci_ep_data_transfer.memcpy.WRITE_TEST ...
#            OK  pci_ep_data_transfer.memcpy.WRITE_TEST
ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST
#  RUN           pci_ep_data_transfer.memcpy.COPY_TEST ...
#            OK  pci_ep_data_transfer.memcpy.COPY_TEST
ok 13 pci_ep_data_transfer.memcpy.COPY_TEST
# PASSED: 13 / 13 tests passed.
# 7 skipped test(s) detected. Consider enabling relevant config options to improve coverage.
# Totals: pass:6 fail:0 xfail:0 xpass:0 skip:7 error:0

lspci output displays all three BARs with this series,

0005:01:00.0 Unassigned class [ff00]: NVIDIA Corporation Device 229b
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0
        Interrupt: pin A routed to IRQ 165
        IOMMU group: 13
        Region 0: Memory at 2b28001000 (64-bit, non-prefetchable) [size=256]
        Region 2: Memory at 2800000000 (64-bit, prefetchable) [size=128K]
        Region 4: Memory at 2b28000000 (64-bit, non-prefetchable) [size=4K]

Manikanta Maddireddy (4):
  PCI: endpoint: Add reserved region type for MSI-X Table and PBA
  PCI: tegra194: Make BAR0 programmable and remove 1MB size limit
  PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit
    BAR_RESERVED
  misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table
    entries

 drivers/misc/pci_endpoint_test.c           | 13 +++++++
 drivers/pci/controller/dwc/pcie-tegra194.c | 40 ++++++++++++++++++----
 include/linux/pci-epc.h                    |  2 ++
 3 files changed, 49 insertions(+), 6 deletions(-)

-- 
2.34.1

[PATCH 1/4] PCI: endpoint: Add reserved region type for MSI-X Table and PBA

[Manikanta Maddireddy]

Add PCI_EPC_BAR_RSVD_MSIX_CTRL_MMIO to enum pci_epc_bar_rsvd_region_type
so that endpoint controllers can describe hardware-owned MSI-X Table and
PBA (Pending Bit Array) regions behind a BAR_RESERVED BAR.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 include/linux/pci-epc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index c181c6d107b7..89ab7d07c5d6 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -214,6 +214,7 @@ enum pci_epc_bar_type {
 /**
  * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
  * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
+ * @PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM: MSI-X table and PBA structures
  *
  * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
  * reprogrammed by EPF drivers. Some of them still expose fixed subregions that
@@ -221,6 +222,7 @@ enum pci_epc_bar_type {
  */
 enum pci_epc_bar_rsvd_region_type {
 	PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
+	PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM,
 };
 
 /**
-- 
2.34.1

[PATCH 2/4] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit

[Manikanta Maddireddy]

BAR0 is capable of supporting various sizes via DBI2 BAR registers
programmed in dw_pcie_ep_set_bar_programmable(). Remove the 1MB fixed
size from pci_epc_features and set the BAR type to BAR_PROGRAMMABLE.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4a3b50322204..3c84a230dc79 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2000,11 +2000,11 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+/* Tegra EP: BAR0 = 64-bit programmable BAR */
 static const struct pci_epc_features tegra_pcie_epc_features = {
 	.linkup_notifier = true,
 	.msi_capable = true,
-	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
-			.only_64bit = true, },
+	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },
 	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_2] = { .type = BAR_DISABLED, },
 	.bar[BAR_3] = { .type = BAR_DISABLED, },
-- 
2.34.1

[PATCH 3/4] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED

[Manikanta Maddireddy]

Tegra endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
- BAR0+BAR1: EPF test/data (programmable 64-bit BAR)
- BAR2+BAR3: MSI-X table (hardware-backed)
- BAR4+BAR5: DMA registers (hardware-backed)

Update tegra_pcie_epc_features so BAR2 is BAR_RESERVED with
PCI_EPC_BAR_RSVD_MSIX_CTRL_MMIO (128KB), BAR3 is BAR_64BIT_UPPER,
BAR4 is BAR_RESERVED with PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB), and
BAR5 is BAR_64BIT_UPPER. This keeps CONSECUTIVE_BAR_TEST working
while allowing the host to use 64-bit BAR2 (MSI-X) and BAR4 (DMA).

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 38 +++++++++++++++++++---
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 3c84a230dc79..b5397a63461f 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2000,16 +2000,44 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
-/* Tegra EP: BAR0 = 64-bit programmable BAR */
+static const struct pci_epc_bar_rsvd_region tegra194_bar2_rsvd[] = {
+	{
+		/* MSI-X structure */
+		.type = PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM,
+		.offset = 0x0,
+		.size = SZ_128K,
+	},
+};
+
+static const struct pci_epc_bar_rsvd_region tegra194_bar4_rsvd[] = {
+	{
+		/* DMA_CAP (BAR4: DMA Port Logic Structure) */
+		.type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
+		.offset = 0x0,
+		.size = SZ_4K,
+	},
+};
+
+/* Tegra EP: BAR0 = 64-bit programmable BAR,  BAR2 = 64-bit MSI-X table, BAR4 = 64-bit DMA regs. */
 static const struct pci_epc_features tegra_pcie_epc_features = {
 	.linkup_notifier = true,
 	.msi_capable = true,
 	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },
 	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
-	.bar[BAR_2] = { .type = BAR_DISABLED, },
-	.bar[BAR_3] = { .type = BAR_DISABLED, },
-	.bar[BAR_4] = { .type = BAR_DISABLED, },
-	.bar[BAR_5] = { .type = BAR_DISABLED, },
+	.bar[BAR_2] = {
+		.type = BAR_RESERVED,
+		.only_64bit = true,
+		.nr_rsvd_regions = ARRAY_SIZE(tegra194_bar2_rsvd),
+		.rsvd_regions = tegra194_bar2_rsvd,
+	},
+	.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
+	.bar[BAR_4] = {
+		.type = BAR_RESERVED,
+		.only_64bit = true,
+		.nr_rsvd_regions = ARRAY_SIZE(tegra194_bar4_rsvd),
+		.rsvd_regions = tegra194_bar4_rsvd,
+	},
+	.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
 	.align = SZ_64K,
 };
 
-- 
2.34.1

[PATCH 4/4] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries

[Manikanta Maddireddy]

Add PCI device IDs and test data for Tegra194 (0x1ad4) and Tegra234
(0x229b) endpoints so pci_endpoint_test can bind and run on these
controllers (64K BAR alignment).

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/misc/pci_endpoint_test.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index f166b6fea698..43545dbad26f 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -106,6 +106,9 @@
 
 #define PCI_DEVICE_ID_ROCKCHIP_RK3588		0x3588
 
+#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP	0x1ad4
+#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP	0x229b
+
 static DEFINE_IDA(pci_endpoint_test_ida);
 
 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -1202,6 +1205,10 @@ static const struct pci_endpoint_test_data rk3588_data = {
 	.alignment = SZ_64K,
 };
 
+static const struct pci_endpoint_test_data tegra_ep_data = {
+	.alignment = SZ_64K,
+};
+
 /*
  * If the controller's Vendor/Device ID are programmable, you may be able to
  * use one of the existing entries for testing instead of adding a new one.
@@ -1246,6 +1253,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
 	  .driver_data = (kernel_ulong_t)&rk3588_data,
 	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),
+	  .driver_data = (kernel_ulong_t)&tegra_ep_data,
+	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),
+	  .driver_data = (kernel_ulong_t)&tegra_ep_data,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
-- 
2.34.1

Re: [PATCH 1/4] PCI: endpoint: Add reserved region type for MSI-X Table and PBA

[Niklas Cassel]

On Mon, Feb 23, 2026 at 01:04:53AM +0530, Manikanta Maddireddy wrote:
> Add PCI_EPC_BAR_RSVD_MSIX_CTRL_MMIO to enum pci_epc_bar_rsvd_region_type
> so that endpoint controllers can describe hardware-owned MSI-X Table and
> PBA (Pending Bit Array) regions behind a BAR_RESERVED BAR.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  include/linux/pci-epc.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index c181c6d107b7..89ab7d07c5d6 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -214,6 +214,7 @@ enum pci_epc_bar_type {
>  /**
>   * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
>   * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
> + * @PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM: MSI-X table and PBA structures

Is it perhaps better to have MSI-X table and PBA structure as two separate
entries?

E.g. in RK3588 TRM:

BAR4: MSI-X Table
Offset: 0x4000
MSI-X Table

BAR4: MSI-X PBA
Offset: 0x5000
MSI-X PBA

Because, at least on RK3588, these seem to have two separate fixed offsets.

Yes, you can probably read PCI_MSIX_TABLE_SIZE in the MSI-X capability.

But, AFAICT from reading the RK3588 TRM (regardless of the size of the
MSI-X table), the PBA is always at offset 0x5000.


Kind regards,
Niklas


>   *
>   * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
>   * reprogrammed by EPF drivers. Some of them still expose fixed subregions that
> @@ -221,6 +222,7 @@ enum pci_epc_bar_type {
>   */
>  enum pci_epc_bar_rsvd_region_type {
>  	PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
> +	PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM,
>  };
>  
>  /**
> -- 
> 2.34.1
> 

Re: [PATCH 2/4] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit

[Niklas Cassel]

On Mon, Feb 23, 2026 at 01:04:54AM +0530, Manikanta Maddireddy wrote:
> BAR0 is capable of supporting various sizes via DBI2 BAR registers
> programmed in dw_pcie_ep_set_bar_programmable(). Remove the 1MB fixed
> size from pci_epc_features and set the BAR type to BAR_PROGRAMMABLE.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4a3b50322204..3c84a230dc79 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2000,11 +2000,11 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  	return 0;
>  }
>  
> +/* Tegra EP: BAR0 = 64-bit programmable BAR */
>  static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.linkup_notifier = true,
>  	.msi_capable = true,
> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
> -			.only_64bit = true, },
> +	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },

If BAR_PROGRAMMABLE, you don't strictly need .type at all, as
BAR_PROGRAMMABLE is (and has always been) the default, defined as value 0.
(So you could simply drop .type from the initializer.)



Are you sure that the BAR is Programmable and not Resizable though?
Because historically, a lot of BARs were defined as Fixed size BARs with
size 1 MB, because there was no Resizable BAR support yet
(the minimum size of a Resizable BAR is 1 MB).

See e.g.:
6a6b66f7e607 ("PCI: keystone: Describe Resizable BARs as Resizable BARs")
aba2b17810d7 ("PCI: dw-rockchip: Describe Resizable BARs as Resizable BARs")


One easy way to check this is to just do (on the host side):

# lspci -s 0000:01:00.0  -vvv | grep Resizable
        Capabilities: [2e8 v1] Physical Resizable BAR

Here you see e.g. that RK3588 based EP implements the "Physical Resizable BAR"
capability.
(Replace 0000:01:00.0 with the BDF of your Tegra based EP.)


Kind regards,
Niklas

Re: [PATCH 3/4] PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED

[Niklas Cassel]

On Mon, Feb 23, 2026 at 01:04:55AM +0530, Manikanta Maddireddy wrote:
> Tegra endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
> - BAR0+BAR1: EPF test/data (programmable 64-bit BAR)
> - BAR2+BAR3: MSI-X table (hardware-backed)
> - BAR4+BAR5: DMA registers (hardware-backed)
> 
> Update tegra_pcie_epc_features so BAR2 is BAR_RESERVED with
> PCI_EPC_BAR_RSVD_MSIX_CTRL_MMIO (128KB), BAR3 is BAR_64BIT_UPPER,
> BAR4 is BAR_RESERVED with PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB), and
> BAR5 is BAR_64BIT_UPPER. This keeps CONSECUTIVE_BAR_TEST working
> while allowing the host to use 64-bit BAR2 (MSI-X) and BAR4 (DMA).
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 38 +++++++++++++++++++---
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 3c84a230dc79..b5397a63461f 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2000,16 +2000,44 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  	return 0;
>  }
>  
> -/* Tegra EP: BAR0 = 64-bit programmable BAR */
> +static const struct pci_epc_bar_rsvd_region tegra194_bar2_rsvd[] = {
> +	{
> +		/* MSI-X structure */
> +		.type = PCI_EPC_BAR_RSVD_MSIX_CTRL_RAM,
> +		.offset = 0x0,
> +		.size = SZ_128K,
> +	},
> +};
> +
> +static const struct pci_epc_bar_rsvd_region tegra194_bar4_rsvd[] = {
> +	{
> +		/* DMA_CAP (BAR4: DMA Port Logic Structure) */
> +		.type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
> +		.offset = 0x0,
> +		.size = SZ_4K,
> +	},
> +};
> +
> +/* Tegra EP: BAR0 = 64-bit programmable BAR,  BAR2 = 64-bit MSI-X table, BAR4 = 64-bit DMA regs. */
>  static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.linkup_notifier = true,
>  	.msi_capable = true,
>  	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },
>  	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> -	.bar[BAR_2] = { .type = BAR_DISABLED, },
> -	.bar[BAR_3] = { .type = BAR_DISABLED, },
> -	.bar[BAR_4] = { .type = BAR_DISABLED, },
> -	.bar[BAR_5] = { .type = BAR_DISABLED, },
> +	.bar[BAR_2] = {
> +		.type = BAR_RESERVED,
> +		.only_64bit = true,

Here you define a BAR of type BAR_RESERVED as .only_64bit.

In include/linux/pci-epc.h:
"only_64bit should not be set on a BAR of type BAR_RESERVED.
(If BARx is a 64-bit BAR that an EPF driver is not allowed to
reprogram, then both BARx and BARx+1 must be set to type
BAR_RESERVED.)"


However, if we look at pci_epc_get_next_free_bar(), it will
handle this perfectly fine already.


So I think it does make sense to allow a RERSERVED_BAR to have
only_64bit = true after all.

(E.g. if we in the future want to disable the RESERVED BAR,
it is good to know that it is a 64-bit BAR, even if it is
RESERVED, because if we disable it, the disable function will
know that it will need to clear the upper bits/adjecent BAR as
well.)

Perhaps just create a new commit in your series which simply removes
does:

@@ -243,11 +243,6 @@ struct pci_epc_bar_rsvd_region {
  *             should be configured as 32-bit or 64-bit, the EPF driver must
  *             configure this BAR as 64-bit. Additionally, the BAR succeeding
  *             this BAR must be set to type BAR_64BIT_UPPER.
- *
- *             only_64bit should not be set on a BAR of type BAR_RESERVED.
- *             (If BARx is a 64-bit BAR that an EPF driver is not allowed to
- *             reprogram, then both BARx and BARx+1 must be set to type
- *             BAR_RESERVED.)
  * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
  * @rsvd_regions: fixed subregions behind BAR_RESERVED
  */

from include/linux/pci-epc.h.

With the motivation that if the BAR is 64-bit by default, and it is
reserved, it makes sense to set it as only64bit, because that is the most
accurate description, and even if we don't have a disable_bar() function
to disable a BAR that we have not called set_bar() on today (so we can't
disable a reserved BAR today), we might implement it in the future, and
then the disable_bar() function will need to clear the adjecent BAR as
well, so better to describe it as correctly as possible already.


Kind regards,
Niklas

Re: [PATCH 4/4] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries

[Niklas Cassel]

On Mon, Feb 23, 2026 at 01:04:56AM +0530, Manikanta Maddireddy wrote:
> Add PCI device IDs and test data for Tegra194 (0x1ad4) and Tegra234
> (0x229b) endpoints so pci_endpoint_test can bind and run on these
> controllers (64K BAR alignment).
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>  drivers/misc/pci_endpoint_test.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> index f166b6fea698..43545dbad26f 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -106,6 +106,9 @@
>  
>  #define PCI_DEVICE_ID_ROCKCHIP_RK3588		0x3588
>  
> +#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP	0x1ad4
> +#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP	0x229b
> +
>  static DEFINE_IDA(pci_endpoint_test_ida);
>  
>  #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
> @@ -1202,6 +1205,10 @@ static const struct pci_endpoint_test_data rk3588_data = {
>  	.alignment = SZ_64K,
>  };
>  
> +static const struct pci_endpoint_test_data tegra_ep_data = {
> +	.alignment = SZ_64K,
> +};

An explcit .alignment is not needed anymore, it was only needed before we
introduced capabilities. New entries should be added without an explicit
alignment, since it will be provided by the capabilties register.


> +
>  /*
>   * If the controller's Vendor/Device ID are programmable, you may be able to
>   * use one of the existing entries for testing instead of adding a new one.
> @@ -1246,6 +1253,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
>  	{ PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
>  	  .driver_data = (kernel_ulong_t)&rk3588_data,
>  	},
> +	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),
> +	  .driver_data = (kernel_ulong_t)&tegra_ep_data,
> +	},
> +	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),
> +	  .driver_data = (kernel_ulong_t)&tegra_ep_data,
> +	},


Just add the PCI device and vendor ID without providing any additional
driver data. See e.g. these existing entries:


	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_IMX8),},

        { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
        { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
        { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
        { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
        { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),




Kind regards,
Niklas

Re: [PATCH 4/4] misc: pci_endpoint_test: Add Tegra194 and Tegra234 device table entries

[Niklas Cassel]

On Wed, Feb 25, 2026 at 06:59:02PM +0100, Niklas Cassel wrote:
> On Mon, Feb 23, 2026 at 01:04:56AM +0530, Manikanta Maddireddy wrote:
> > Add PCI device IDs and test data for Tegra194 (0x1ad4) and Tegra234
> > (0x229b) endpoints so pci_endpoint_test can bind and run on these
> > controllers (64K BAR alignment).
> > 
> > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > ---
> >  drivers/misc/pci_endpoint_test.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> > index f166b6fea698..43545dbad26f 100644
> > --- a/drivers/misc/pci_endpoint_test.c
> > +++ b/drivers/misc/pci_endpoint_test.c
> > @@ -106,6 +106,9 @@
> >  
> >  #define PCI_DEVICE_ID_ROCKCHIP_RK3588		0x3588
> >  
> > +#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP	0x1ad4
> > +#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP	0x229b
> > +
> >  static DEFINE_IDA(pci_endpoint_test_ida);
> >  
> >  #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
> > @@ -1202,6 +1205,10 @@ static const struct pci_endpoint_test_data rk3588_data = {
> >  	.alignment = SZ_64K,
> >  };
> >  
> > +static const struct pci_endpoint_test_data tegra_ep_data = {
> > +	.alignment = SZ_64K,
> > +};
> 
> An explcit .alignment is not needed anymore, it was only needed before we
> introduced capabilities. New entries should be added without an explicit
> alignment, since it will be provided by the capabilties register.

Sorry, small clarification:
Allocating extra large buffers on the host side (.alignment) is not needed
anymore, since pci-epf-test (the endpoint side) nowadays can do unaligned
accesses using pci_epc_mem_map()/unmap().

See:
ce1dfe6d3289 ("PCI: endpoint: Introduce pci_epc_mem_map()/unmap()")
08cac1006bfc ("PCI: endpoint: test: Use pci_epc_mem_map/unmap()")
8a02612f8566 ("PCI: endpoint: pci-epf-test: Add support for capabilities")


Kind regards,
Niklas

Re: [PATCH 2/4] PCI: tegra194: Make BAR0 programmable and remove 1MB size limit

[Manikanta Maddireddy]

On 25/02/26 11:01 pm, Niklas Cassel wrote:
> On Mon, Feb 23, 2026 at 01:04:54AM +0530, Manikanta Maddireddy wrote:
>> BAR0 is capable of supporting various sizes via DBI2 BAR registers
>> programmed in dw_pcie_ep_set_bar_programmable(). Remove the 1MB fixed
>> size from pci_epc_features and set the BAR type to BAR_PROGRAMMABLE.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 4a3b50322204..3c84a230dc79 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -2000,11 +2000,11 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>   	return 0;
>>   }
>>   
>> +/* Tegra EP: BAR0 = 64-bit programmable BAR */
>>   static const struct pci_epc_features tegra_pcie_epc_features = {
>>   	.linkup_notifier = true,
>>   	.msi_capable = true,
>> -	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
>> -			.only_64bit = true, },
>> +	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },
> 
> If BAR_PROGRAMMABLE, you don't strictly need .type at all, as
> BAR_PROGRAMMABLE is (and has always been) the default, defined as value 0.
> (So you could simply drop .type from the initializer.)
> 
> 
> 
> Are you sure that the BAR is Programmable and not Resizable though?

Yes, Tegra194 PCIe doesn't support Resizable BAR capability.
However, during Endpoint initialization, EPF driver can set
desired BAR0 size once. I will update the commit message
with this explanation.

Thanks,
Manikanta

> Because historically, a lot of BARs were defined as Fixed size BARs with
> size 1 MB, because there was no Resizable BAR support yet
> (the minimum size of a Resizable BAR is 1 MB).
> 
> See e.g.:
> 6a6b66f7e607 ("PCI: keystone: Describe Resizable BARs as Resizable BARs")
> aba2b17810d7 ("PCI: dw-rockchip: Describe Resizable BARs as Resizable BARs")
> 
> 
> One easy way to check this is to just do (on the host side):
> 
> # lspci -s 0000:01:00.0  -vvv | grep Resizable
>          Capabilities: [2e8 v1] Physical Resizable BAR
> 
> Here you see e.g. that RK3588 based EP implements the "Physical Resizable BAR"
> capability.
> (Replace 0000:01:00.0 with the BDF of your Tegra based EP.)
> 
> 
> Kind regards,
> Niklas
> 

-- 
nvpublic