Re: [PATCH v2] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status

[Lukas Wunner <lukas@wunner.de>]

On Fri, Feb 13, 2026 at 03:14:28PM -0800, Kuppuswamy Sathyanarayanan wrote:
> On Intel Catlow Lake platforms, PCH PCIe root ports do not reliably
> update PME status registers (PME Status and PME Requester_ID in the
> Root Status register) during D3hot to D0 transitions, even though PME
> interrupts are delivered correctly.

Hm, so in theory we could amend the PME driver to walk the bus below the
Root Port and see if anything has PME_Status set in the PMCSR register.

But the PME interrupt is shared with hotplug, bandwidth control etc,
so we'd end up gratuitouly (and frequently) runtime resuming switches
below the Root Port to see if there's anything below which is requesting
wakeup.

So just keeping the Root Port runtime resumed all the time, as this
patch does, is still a better approach IMO.

I'm wondering though if this causes a power regression.  Does keeping
the Root Port in D0 prevent the Package from entering a lower power
state?  Or is this irrelevant because the PCH is a different chip
or tile?

If you respin, please cc Rafael and linux-pm@vger.kernel.org to see
if PM maintainers have any objections.

> +++ b/drivers/pci/quirks.c

Since this is x86-specific, it could live in arch/x86/kernel/quirks.c
or arch/x86/pci/fixup.c to prevent being compiled in on other arches.

(I don't know why x86 quirks are spread out across two different files
and there doesn't seem to be a consistent rule which one to pick.)

Otherwise this is
Reviewed-by: Lukas Wunner <lukas@wunner.de>

Thanks,

Lukas