[PATCH 0/4] ARM: dts: imx: {bx50v3,b850v3}: Update device trees

[PATCH 0/4] ARM: dts: imx: {bx50v3,b850v3}: Update device trees

[Ian Ray]

Configure PHY speed and mode.
Configure b850v3 gpio4 line name.
Disable b850v3 usdhc4 interface.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
---
Ian Ray (4):
  ARM: dts: imx: bx50v3: Configure switch PHY max-speed
  ARM: dts: imx: bx50v3: Configure phy-mode
  ARM: dts: imx: b850v3: Define GPIO line names
  ARM: dts: imx: b850v3: Disable usdhc4

 arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts  |  1 +
 arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts  |  1 +
 arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts  | 17 +++++++++++++++++
 arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi |  4 ++++
 4 files changed, 23 insertions(+)

-- 
2.49.0

[PATCH 1/4] ARM: dts: imx: bx50v3: Configure switch PHY max-speed

[Ian Ray]

Configure maximum speed for the switch PHYs according to the electrical
connections from PHY to RJ45 connector.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
---
 arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
index 1e2266a2368b..2c8d2ab8cda1 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi
@@ -124,24 +124,28 @@ switchphy0: switchphy@0 {
 					reg = <0>;
 					interrupt-parent = <&switch>;
 					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+					max-speed = <100>; /* only 100Mbit/s lanes are routed */
 				};
 
 				switchphy1: switchphy@1 {
 					reg = <1>;
 					interrupt-parent = <&switch>;
 					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+					max-speed = <100>; /* only 100Mbit/s lanes are routed */
 				};
 
 				switchphy2: switchphy@2 {
 					reg = <2>;
 					interrupt-parent = <&switch>;
 					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+					max-speed = <100>; /* only 100Mbit/s lanes are routed */
 				};
 
 				switchphy3: switchphy@3 {
 					reg = <3>;
 					interrupt-parent = <&switch>;
 					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+					max-speed = <100>; /* only 100Mbit/s lanes are routed */
 				};
 
 				switchphy4: switchphy@4 {
-- 
2.49.0

[PATCH 2/4] ARM: dts: imx: bx50v3: Configure phy-mode

[Ian Ray]

Set `phy-mode' on network switch CPU ports to eliminate a warning.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
---
 arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts | 1 +
 arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts | 1 +
 arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
index d994b32ad825..7326b8ad08cb 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
@@ -140,6 +140,7 @@ port@3 {
 	port@4 {
 		reg = <4>;
 		label = "cpu";
+		phy-mode = "gmii";
 		ethernet = <&switch_nic>;
 		phy-handle = <&switchphy4>;
 	};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
index b0d345f5d071..9a43935be11c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
@@ -139,6 +139,7 @@ port@3 {
 	port@4 {
 		reg = <4>;
 		label = "cpu";
+		phy-mode = "gmii";
 		ethernet = <&switch_nic>;
 		phy-handle = <&switchphy4>;
 	};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
index cad112e05475..e7ccdcba2d5c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
@@ -286,6 +286,7 @@ port@3 {
 	port@4 {
 		reg = <4>;
 		label = "cpu";
+		phy-mode = "gmii";
 		ethernet = <&switch_nic>;
 		phy-handle = <&switchphy4>;
 	};
-- 
2.49.0

[PATCH 3/4] ARM: dts: imx: b850v3: Define GPIO line names

[Ian Ray]

Define GPIO line names for gpio4.

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
---
 arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
index e7ccdcba2d5c..30181b5132a9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
@@ -72,6 +72,18 @@ lvds0_out: endpoint {
 	};
 };
 
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "PWGIN", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "",
+		"", "", "", "";
+};
+
 &i2c2 {
 	pca9547_ddc: mux@70 {
 		compatible = "nxp,pca9547";
-- 
2.49.0

[PATCH 4/4] ARM: dts: imx: b850v3: Disable usdhc4

[Ian Ray]

Disable the unused interface, to fix a log message.

```
mmc3: Failed to initialize a non-removable card
```

Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
---
 arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
index 30181b5132a9..a030b26e06b4 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts
@@ -303,3 +303,7 @@ port@4 {
 		phy-handle = <&switchphy4>;
 	};
 };
+
+&usdhc4 {
+	status = "disabled";
+};
-- 
2.49.0

Re: [PATCH 2/4] ARM: dts: imx: bx50v3: Configure phy-mode

[Daniel Baluta]

On 2/17/26 14:59, Ian Ray wrote:
> Set `phy-mode' on network switch CPU ports to eliminate a warning.

Can you mention in the commit message what is the warning

and how did you get it?

Re: [PATCH 2/4] ARM: dts: imx: bx50v3: Configure phy-mode

[Ian Ray]

On Tue, Feb 17, 2026 at 03:08:17PM +0200, Daniel Baluta wrote:
> CAUTION: This email originated from outside of GE HealthCare. Only open links or attachments if you trust the sender. Report suspicious emails using Outlook’s “Report” button.
> 
> On 2/17/26 14:59, Ian Ray wrote:
> > Set `phy-mode' on network switch CPU ports to eliminate a warning.
> 
> Can you mention in the commit message what is the warning

Apologies for not being clearer. (Checks notes.) The warning was:

-- >8 --
mv88e6085 gpio-0:00: OF node /mdio-gpio/switch@0/ports/port@4 of CPU port 4 lacks the required "phy-mode" property
-- >8 --

I will prepare a V2.

> 
> and how did you get it?
> 

Re: [PATCH 3/4] ARM: dts: imx: b850v3: Define GPIO line names

[Ian Ray]

On Tue, Feb 17, 2026 at 03:23:02PM +0200, Daniel Baluta wrote:
> CAUTION: This email originated from outside of GE HealthCare. Only open links or attachments if you trust the sender. Report suspicious emails using Outlook’s “Report” button.
> 
> On 2/17/26 14:59, Ian Ray wrote:
> > @@ -72,6 +72,18 @@ lvds0_out: endpoint {
> >         };
> >  };
> >
> > +&gpio4 {
> > +       gpio-line-names =
> > +               "", "", "", "",
> > +               "", "", "", "",
> > +               "", "", "", "",
> > +               "", "", "PWGIN", "",
> > +               "", "", "", "",
> > +               "", "", "", "",
> > +               "", "", "", "",
> > +               "", "", "", "";
> > +};
> 
> Looking at my latest version of code this node should be a little bit up in the
> 
> file to preserve the alphabetical sorting of references modification.

Good catch, thanks!  Will include in V2.

> 
> e.g
> 
> +&gpio4 {
> 
> ... then
> 
> comes
> 
> &ldb {
> 
> 
> etc.
> 
> 

Re: [PATCH 3/4] ARM: dts: imx: b850v3: Define GPIO line names

[Daniel Baluta]

On 2/17/26 14:59, Ian Ray wrote:
> @@ -72,6 +72,18 @@ lvds0_out: endpoint {
>         };
>  };
>
> +&gpio4 {
> +       gpio-line-names =
> +               "", "", "", "",
> +               "", "", "", "",
> +               "", "", "", "",
> +               "", "", "PWGIN", "",
> +               "", "", "", "",
> +               "", "", "", "",
> +               "", "", "", "",
> +               "", "", "", "";
> +};

Looking at my latest version of code this node should be a little bit up in the

file to preserve the alphabetical sorting of references modification.

e.g

+&gpio4 {

... then

comes

&ldb {


etc.

Re: [PATCH 1/4] ARM: dts: imx: bx50v3: Configure switch PHY max-speed

[Andrew Lunn]

On Tue, Feb 17, 2026 at 02:59:48PM +0200, Ian Ray wrote:
> Configure maximum speed for the switch PHYs according to the electrical
> connections from PHY to RJ45 connector.

Are you saying only 2 of the 4 pairs are connected to the RJ45
connector? And i assume you are using a 1G capable PHY?

> +					max-speed = <100>; /* only 100Mbit/s lanes are routed */

lanes generally refer to SERDES interfaces. For twisted pairs we use
pairs.

	Andrew

Re: [PATCH 2/4] ARM: dts: imx: bx50v3: Configure phy-mode

[Andrew Lunn]

On Tue, Feb 17, 2026 at 02:59:49PM +0200, Ian Ray wrote:
> Set `phy-mode' on network switch CPU ports to eliminate a warning.
> 
> Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
> ---
>  arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts | 1 +
>  arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts | 1 +
>  arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
> index d994b32ad825..7326b8ad08cb 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
> @@ -140,6 +140,7 @@ port@3 {
>  	port@4 {
>  		reg = <4>;
>  		label = "cpu";
> +		phy-mode = "gmii";

Are the PHYs external to the switch?

>  	port@4 {
>  		reg = <4>;
>  		label = "cpu";
> +		phy-mode = "gmii";
>  		ethernet = <&switch_nic>;
>  		phy-handle = <&switchphy4>;

You have back to back PHYs on the CPU port? This is not wrong, but
unusual.

	Andrew

Re: [PATCH 1/4] ARM: dts: imx: bx50v3: Configure switch PHY max-speed

[Ian Ray]

On Tue, Feb 17, 2026 at 03:53:08PM +0100, Andrew Lunn wrote:
> CAUTION: This email originated from outside of GE HealthCare. Only open links or attachments if you trust the sender. Report suspicious emails using Outlook’s “Report” button.
> 
> On Tue, Feb 17, 2026 at 02:59:48PM +0200, Ian Ray wrote:
> > Configure maximum speed for the switch PHYs according to the electrical
> > connections from PHY to RJ45 connector.
> 
> Are you saying only 2 of the 4 pairs are connected to the RJ45
> connector? And i assume you are using a 1G capable PHY?

That's right.

> 
> > +                                     max-speed = <100>; /* only 100Mbit/s lanes are routed */
> 
> lanes generally refer to SERDES interfaces. For twisted pairs we use
> pairs.

Thanks for the clarification: I will send a V3 in two weeks time.

> 
>         Andrew

Re: [PATCH 2/4] ARM: dts: imx: bx50v3: Configure phy-mode

[Ian Ray]

On Tue, Feb 17, 2026 at 03:58:42PM +0100, Andrew Lunn wrote:
> CAUTION: This email originated from outside of GE HealthCare. Only open links or attachments if you trust the sender. Report suspicious emails using Outlook’s “Report” button.
> 
> On Tue, Feb 17, 2026 at 02:59:49PM +0200, Ian Ray wrote:
> > Set `phy-mode' on network switch CPU ports to eliminate a warning.
> >
> > Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
> > ---
> >  arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts | 1 +
> >  arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts | 1 +
> >  arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts | 1 +
> >  3 files changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
> > index d994b32ad825..7326b8ad08cb 100644
> > --- a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
> > +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts
> > @@ -140,6 +140,7 @@ port@3 {
> >       port@4 {
> >               reg = <4>;
> >               label = "cpu";
> > +             phy-mode = "gmii";
> 
> Are the PHYs external to the switch?

Yes, port 4 is connected to an I210.

> 
> >       port@4 {
> >               reg = <4>;
> >               label = "cpu";
> > +             phy-mode = "gmii";
> >               ethernet = <&switch_nic>;
> >               phy-handle = <&switchphy4>;
> 
> You have back to back PHYs on the CPU port? This is not wrong, but
> unusual.

No, the patch sets `phy-mode' on three different boards.  (If I
understand your question correctly.)

Thanks,
Ian

> 
>         Andrew