[PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework

[PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework

[Manikanta Maddireddy]

When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the
EPF does not allocate backing memory. The host-side pci_endpoint_test driver
still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to
BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks
CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only
BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no
longer available for real use (e.g. host DMA via BAR4).

This series addresses that by:

1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.
   BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may
   leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is
   for unused BARs that the EPC must disable in .init() and the EPF must not
   use. pci_epc_get_next_free_bar() treats both as not free.

2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:
   BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.
   Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay
   enabled so the host can use MSI-X and DMA.

3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the
   destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5
   (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)
   to the pci_endpoint_test_tbl so the host driver can bind and run tests
   without corrupting MSI-X or DMA registers.

4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint
   (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of
   64-bit BAR0 and BAR2.

With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit
BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.

pci_endpoint_test results on Tegra234 SoC,

$ ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma
TAP version 13
1..13
 Starting 13 tests from 8 test cases.
  RUN           pci_ep_bar.BAR0.BAR_TEST ...
            OK  pci_ep_bar.BAR0.BAR_TEST
ok 1 pci_ep_bar.BAR0.BAR_TEST
  RUN           pci_ep_bar.BAR1.BAR_TEST ...
            OK  pci_ep_bar.BAR1.BAR_TEST
ok 2 pci_ep_bar.BAR1.BAR_TEST
  RUN           pci_ep_bar.BAR2.BAR_TEST ...
            OK  pci_ep_bar.BAR2.BAR_TEST
ok 3 pci_ep_bar.BAR2.BAR_TEST
  RUN           pci_ep_bar.BAR3.BAR_TEST ...
            OK  pci_ep_bar.BAR3.BAR_TEST
ok 4 pci_ep_bar.BAR3.BAR_TEST
  RUN           pci_ep_bar.BAR4.BAR_TEST ...
            OK  pci_ep_bar.BAR4.BAR_TEST
ok 5 pci_ep_bar.BAR4.BAR_TEST
  RUN           pci_ep_bar.BAR5.BAR_TEST ...
            OK  pci_ep_bar.BAR5.BAR_TEST
ok 6 pci_ep_bar.BAR5.BAR_TEST
  RUN           pci_ep_basic.CONSECUTIVE_BAR_TEST ...
            OK  pci_ep_basic.CONSECUTIVE_BAR_TEST
ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST
  RUN           pci_ep_basic.LEGACY_IRQ_TEST ...
            OK  pci_ep_basic.LEGACY_IRQ_TEST
ok 8 pci_ep_basic.LEGACY_IRQ_TEST
  RUN           pci_ep_basic.MSI_TEST ...
      SKIP      MSI17 is disabled
            OK  pci_ep_basic.MSI_TEST
ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled
  RUN           pci_ep_basic.MSIX_TEST ...
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X1
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X2
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X3
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X4
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X5
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X6
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X7
 pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
 pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X8
      SKIP      MSI-X9 is disabled
            OK  pci_ep_basic.MSIX_TEST
ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled
  RUN           pci_ep_data_transfer.memcpy.READ_TEST ...
            OK  pci_ep_data_transfer.memcpy.READ_TEST
ok 11 pci_ep_data_transfer.memcpy.READ_TEST
  RUN           pci_ep_data_transfer.memcpy.WRITE_TEST ...
            OK  pci_ep_data_transfer.memcpy.WRITE_TEST
ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST
  RUN           pci_ep_data_transfer.memcpy.COPY_TEST ...
            OK  pci_ep_data_transfer.memcpy.COPY_TEST
ok 13 pci_ep_data_transfer.memcpy.COPY_TEST
 PASSED: 13 / 13 tests passed.
 2 skipped test(s) detected. Consider enabling relevant config options to improve coverage.
 Totals: pass:11 fail:0 xfail:0 xpass:0 skip:2 error:0

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Manikanta Maddireddy (4):
      PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics
      PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode
      misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs
      PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5

 drivers/misc/pci_endpoint_test.c              | 34 ++++++++++++++++++++++++---
 drivers/pci/controller/dwc/pcie-tegra194.c    | 26 +++++++++++---------
 drivers/pci/controller/dwc/pcie-uniphier-ep.c |  8 +++----
 drivers/pci/endpoint/pci-epc-core.c           |  5 ++--
 include/linux/pci-epc.h                       | 13 ++++++++--
 5 files changed, 64 insertions(+), 22 deletions(-)
---
base-commit: 6f54fb70124423ec417b5efe81f8ced5b9891d62
change-id: 20260217-master-27db95eb02bd

Best regards,
-- 
Manikanta Maddireddy <mmaddireddy@nvidia.com>

[PATCH 1/4] PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics

[Manikanta Maddireddy]

Add BAR_DISABLED to enum pci_epc_bar_type for BARs that are unused: the
EPC must disable them in .init(), the EPF must not use them, and they
are not returned by pci_epc_get_next_free_bar().

Document BAR_RESERVED for two uses: (1) HW-backed BARs (e.g. MSI-X
table, DMA regs) that the EPC may leave enabled for the host, and
(2) the second register of a 64-bit BAR (high 32 bits) when the
preceding BAR has only_64bit set.

Update pci_epc_get_next_free_bar() to treat both BAR_RESERVED and
BAR_DISABLED as not free so EPF drivers do not allocate or use
these BARs.

This allows EPC drivers such as Tegra194 to keep HW-backed 64-bit
BARs (MSI-X, DMA) enabled while still preventing EPF from using
reserved or disabled BARs.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/endpoint/pci-epc-core.c |  5 +++--
 include/linux/pci-epc.h             | 13 +++++++++++--
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index ca7f19cc973a..1d6b04ac4fc5 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -103,8 +103,9 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
 		bar++;
 
 	for (i = bar; i < PCI_STD_NUM_BARS; i++) {
-		/* If the BAR is not reserved, return it. */
-		if (epc_features->bar[i].type != BAR_RESERVED)
+		/* If the BAR is not reserved or disabled, return it. */
+		if (epc_features->bar[i].type != BAR_RESERVED &&
+		    epc_features->bar[i].type != BAR_DISABLED)
 			return i;
 	}
 
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 4286bfdbfdfa..9b3714a0dafc 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -191,13 +191,21 @@ struct pci_epc {
  * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
  *		   NOTE: An EPC driver can currently only set a single supported
  *		   size.
- * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
+ * @BAR_RESERVED: The BAR should not be touched by an EPF driver. Used for:
+ *		  (1) HW-backed BARs (e.g. MSI-X table, DMA regs) that the EPC
+ *		      may leave enabled for the host; (2) the second register
+ *		      of a 64-bit BAR (the high 32 bits), when the preceding
+ *		      BAR has only_64bit set.
+ * @BAR_DISABLED: The BAR is unused; the EPC must disable it in .init(); the
+ *		  EPF must not use it; it is not returned by
+ *		  pci_epc_get_next_free_bar().
  */
 enum pci_epc_bar_type {
 	BAR_PROGRAMMABLE = 0,
 	BAR_FIXED,
 	BAR_RESIZABLE,
 	BAR_RESERVED,
+	BAR_DISABLED,
 };
 
 /**
@@ -212,7 +220,8 @@ enum pci_epc_bar_type {
  *		only_64bit should not be set on a BAR of type BAR_RESERVED.
  *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
  *		touch, then both BARx and BARx+1 must be set to type
- *		BAR_RESERVED.)
+ *		BAR_RESERVED. BAR_RESERVED is used both for HW-backed BARs and
+ *		for the high half of a 64-bit BAR.)
  */
 struct pci_epc_bar_desc {
 	enum pci_epc_bar_type type;

-- 
2.34.1

[PATCH 2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode

[Manikanta Maddireddy]

Tegra194 endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
- BAR0+BAR1: EPF test/data (first 64-bit BAR)
- BAR2+BAR3: MSI-X table (HW-backed)
- BAR4+BAR5: DMA registers (HW-backed)

Update tegra_pcie_epc_features so that BAR0 is BAR_FIXED with only_64bit,
BAR1 is BAR_RESERVED (high half of 64-bit BAR0), BAR2/BAR3 are
BAR_RESERVED with only_64bit on BAR2 (MSI-X), and BAR4/BAR5 are
BAR_RESERVED with only_64bit on BAR4 (DMA).

In tegra_pcie_ep_init(), reset only BAR0 and BAR1 so that the first
64-bit BAR is disabled until the EPF enables it via set_bar. Do not
reset BAR2+BAR3 or BAR4+BAR5 so that MSI-X and DMA remain enabled for
the host.

This keeps CONSECUTIVE_BAR_TEST and DMA tests working while allowing
the host to use 64-bit BAR 2 (MSI-X) and 64-bit BAR 4 (DMA) for real
use.

BAR0 is capabale of supporting various sizes using DBI2 BAR registers
which are programmed in dw_pcie_ep_set_bar_programmable(), remove
1 MB size limit from pci_epc_features.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 1b4fc6a9bed1..6734d1336ef1 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1948,11 +1948,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
 static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
 
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-};
+	/*
+	 * Only reset the first 64-bit BAR (BAR0+BAR1); EPF will enable it via set_bar.
+	 * BAR2+BAR3 (MSI-X table) and BAR4+BAR5 (DMA regs) are HW-backed and must
+	 * stay enabled.
+	 */
+	dw_pcie_ep_reset_bar(pci, BAR_0);
+	dw_pcie_ep_reset_bar(pci, BAR_1);
+}
 
 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
@@ -2009,16 +2013,16 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+/* Tegra194 EP: BAR0 = programmable BAR, BAR2 = MSI-X table, BAR4 = DMA regs. */
 static const struct pci_epc_features tegra_pcie_epc_features = {
 	.linkup_notifier = true,
 	.msi_capable = true,
-	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
-			.only_64bit = true, },
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
-	.bar[BAR_2] = { .type = BAR_RESERVED, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
-	.bar[BAR_4] = { .type = BAR_RESERVED, },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },
+	.bar[BAR_1] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR0 */
+	.bar[BAR_2] = { .type = BAR_RESERVED, .only_64bit = true, },	/* MSI-X table */
+	.bar[BAR_3] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR2 */
+	.bar[BAR_4] = { .type = BAR_RESERVED, .only_64bit = true, },	/* DMA regs */
+	.bar[BAR_5] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR4 */
 	.align = SZ_64K,
 };
 

-- 
2.34.1

[PATCH 3/4] misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs

[Manikanta Maddireddy]

Add an optional bar_skip_mask to pci_endpoint_test_data so that
endpoints with HW-backed BARs (e.g. MSI-X table, DMA regs) can skip
the destructive BAR read/write test on those BARs. When a BAR is
skipped, it is not written or read in the consecutive BAR test, and
PCITEST_BAR ioctl for that BAR returns -EINVAL.

Add Tegra endpoint test data with bar_skip_mask set to skip BAR1
through BAR5 (test only BAR0, the first 64-bit BAR). Add
pci_endpoint_test_tbl entries for NVIDIA Tegra194 EP (device ID
0x1AD4) and Tegra234 EP (device ID 0x229B) so the host test driver
can bind and run tests without corrupting MSI-X or DMA registers.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/misc/pci_endpoint_test.c | 34 +++++++++++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 1c0fd185114f..4c9f02dbc41b 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -100,6 +100,12 @@
 
 #define PCI_DEVICE_ID_ROCKCHIP_RK3588		0x3588
 
+#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP	0x1ad4
+#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP	0x229b
+
+/* BARs 1-5 are HW-backed (MSI-X, DMA) or high half of 64-bit BAR0; skip BAR test */
+#define TEGRA_EP_BAR_SKIP_MASK	(BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
+
 static DEFINE_IDA(pci_endpoint_test_ida);
 
 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -130,11 +136,15 @@ struct pci_endpoint_test {
 	size_t alignment;
 	u32 ep_caps;
 	const char *name;
+	/* Bitmask of BARs to skip in BAR test (bit N set = skip BAR N) */
+	u8 bar_skip_mask;
 };
 
 struct pci_endpoint_test_data {
 	enum pci_barno test_reg_bar;
 	size_t alignment;
+	/* Bitmask of BARs to skip in BAR test (bit N set = skip BAR N) */
+	u8 bar_skip_mask;
 };
 
 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
@@ -393,9 +403,10 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
 	int ret;
 
 	/* Write all BARs in order (without reading). */
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		if (test->bar[bar])
+	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
+		if (test->bar[bar] && !(test->bar_skip_mask & (1 << bar)))
 			pci_endpoint_test_bars_write_bar(test, bar);
+	}
 
 	/*
 	 * Read all BARs in order (without writing).
@@ -404,7 +415,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
 	 * (Reading back the BAR directly after writing can not detect this.)
 	 */
 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
-		if (test->bar[bar]) {
+		if (test->bar[bar] && !(test->bar_skip_mask & (1 << bar))) {
 			ret = pci_endpoint_test_bars_read_bar(test, bar);
 			if (ret)
 				return ret;
@@ -941,6 +952,10 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
 			goto ret;
 		if (is_am654_pci_dev(pdev) && bar == BAR_0)
 			goto ret;
+		if (test->bar_skip_mask & (1 << bar)) {
+			ret = 0;
+			goto ret;
+		}
 		ret = pci_endpoint_test_bar(test, bar);
 		break;
 	case PCITEST_BARS:
@@ -1028,6 +1043,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
 		test_reg_bar = data->test_reg_bar;
 		test->test_reg_bar = test_reg_bar;
 		test->alignment = data->alignment;
+		test->bar_skip_mask = data->bar_skip_mask;
 	}
 
 	init_completion(&test->irq_raised);
@@ -1173,6 +1189,12 @@ static const struct pci_endpoint_test_data rk3588_data = {
 	.alignment = SZ_64K,
 };
 
+static const struct pci_endpoint_test_data tegra_ep_data = {
+	.test_reg_bar = BAR_0,
+	.alignment = SZ_64K,
+	.bar_skip_mask = TEGRA_EP_BAR_SKIP_MASK,
+};
+
 /*
  * If the controller's Vendor/Device ID are programmable, you may be able to
  * use one of the existing entries for testing instead of adding a new one.
@@ -1217,6 +1239,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),
 	  .driver_data = (kernel_ulong_t)&rk3588_data,
 	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),
+	  .driver_data = (kernel_ulong_t)&tegra_ep_data,
+	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),
+	  .driver_data = (kernel_ulong_t)&tegra_ep_data,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);

-- 
2.34.1

[PATCH 4/4] PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5

[Manikanta Maddireddy]

On Uniphier Pro5, BAR_4 and BAR_5 are not the high half of a 64-bit
BAR (BAR_4 has no only_64bit set) and are not HW-backed; they are
unused. Convert them from BAR_RESERVED to BAR_DISABLED. Add comments
for BAR_1 and BAR_3 to clarify they are the high halves of 64-bit
BAR0 and BAR2.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index d6e73811216e..cf5131eec7bf 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -425,11 +425,11 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
 		.msix_capable = false,
 		.align = 1 << 16,
 		.bar[BAR_0] = { .only_64bit = true, },
-		.bar[BAR_1] = { .type = BAR_RESERVED, },
+		.bar[BAR_1] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR0 */
 		.bar[BAR_2] = { .only_64bit = true, },
-		.bar[BAR_3] = { .type = BAR_RESERVED, },
-		.bar[BAR_4] = { .type = BAR_RESERVED, },
-		.bar[BAR_5] = { .type = BAR_RESERVED, },
+		.bar[BAR_3] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR2 */
+		.bar[BAR_4] = { .type = BAR_DISABLED, },	/* unused */
+		.bar[BAR_5] = { .type = BAR_DISABLED, },	/* unused */
 	},
 };
 

-- 
2.34.1

Re: [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework

[Manikanta Maddireddy]

Apologies for sending the email twice. The mailing lists in CC were 
missing in the
first email. I’ve added them and resent it.


Thanks,
Manikanta


On 17/02/26 11:24 am, Manikanta Maddireddy wrote:
> When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the
> EPF does not allocate backing memory. The host-side pci_endpoint_test driver
> still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to
> BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks
> CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only
> BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no
> longer available for real use (e.g. host DMA via BAR4).
>
> This series addresses that by:
>
> 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.
>     BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may
>     leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is
>     for unused BARs that the EPC must disable in .init() and the EPF must not
>     use. pci_epc_get_next_free_bar() treats both as not free.
>
> 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:
>     BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.
>     Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay
>     enabled so the host can use MSI-X and DMA.
>
> 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the
>     destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5
>     (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)
>     to the pci_endpoint_test_tbl so the host driver can bind and run tests
>     without corrupting MSI-X or DMA registers.
>
> 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint
>     (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of
>     64-bit BAR0 and BAR2.
>
> With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit
> BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.
>
> pci_endpoint_test results on Tegra234 SoC,
>
> $ ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma
> TAP version 13
> 1..13
>   Starting 13 tests from 8 test cases.
>    RUN           pci_ep_bar.BAR0.BAR_TEST ...
>              OK  pci_ep_bar.BAR0.BAR_TEST
> ok 1 pci_ep_bar.BAR0.BAR_TEST
>    RUN           pci_ep_bar.BAR1.BAR_TEST ...
>              OK  pci_ep_bar.BAR1.BAR_TEST
> ok 2 pci_ep_bar.BAR1.BAR_TEST
>    RUN           pci_ep_bar.BAR2.BAR_TEST ...
>              OK  pci_ep_bar.BAR2.BAR_TEST
> ok 3 pci_ep_bar.BAR2.BAR_TEST
>    RUN           pci_ep_bar.BAR3.BAR_TEST ...
>              OK  pci_ep_bar.BAR3.BAR_TEST
> ok 4 pci_ep_bar.BAR3.BAR_TEST
>    RUN           pci_ep_bar.BAR4.BAR_TEST ...
>              OK  pci_ep_bar.BAR4.BAR_TEST
> ok 5 pci_ep_bar.BAR4.BAR_TEST
>    RUN           pci_ep_bar.BAR5.BAR_TEST ...
>              OK  pci_ep_bar.BAR5.BAR_TEST
> ok 6 pci_ep_bar.BAR5.BAR_TEST
>    RUN           pci_ep_basic.CONSECUTIVE_BAR_TEST ...
>              OK  pci_ep_basic.CONSECUTIVE_BAR_TEST
> ok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST
>    RUN           pci_ep_basic.LEGACY_IRQ_TEST ...
>              OK  pci_ep_basic.LEGACY_IRQ_TEST
> ok 8 pci_ep_basic.LEGACY_IRQ_TEST
>    RUN           pci_ep_basic.MSI_TEST ...
>        SKIP      MSI17 is disabled
>              OK  pci_ep_basic.MSI_TEST
> ok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled
>    RUN           pci_ep_basic.MSIX_TEST ...
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X1
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X2
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X3
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X4
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X5
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X6
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X7
>   pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)
>   pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X8
>        SKIP      MSI-X9 is disabled
>              OK  pci_ep_basic.MSIX_TEST
> ok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled
>    RUN           pci_ep_data_transfer.memcpy.READ_TEST ...
>              OK  pci_ep_data_transfer.memcpy.READ_TEST
> ok 11 pci_ep_data_transfer.memcpy.READ_TEST
>    RUN           pci_ep_data_transfer.memcpy.WRITE_TEST ...
>              OK  pci_ep_data_transfer.memcpy.WRITE_TEST
> ok 12 pci_ep_data_transfer.memcpy.WRITE_TEST
>    RUN           pci_ep_data_transfer.memcpy.COPY_TEST ...
>              OK  pci_ep_data_transfer.memcpy.COPY_TEST
> ok 13 pci_ep_data_transfer.memcpy.COPY_TEST
>   PASSED: 13 / 13 tests passed.
>   2 skipped test(s) detected. Consider enabling relevant config options to improve coverage.
>   Totals: pass:11 fail:0 xfail:0 xpass:0 skip:2 error:0
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Manikanta Maddireddy (4):
>        PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics
>        PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode
>        misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs
>        PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5
>
>   drivers/misc/pci_endpoint_test.c              | 34 ++++++++++++++++++++++++---
>   drivers/pci/controller/dwc/pcie-tegra194.c    | 26 +++++++++++---------
>   drivers/pci/controller/dwc/pcie-uniphier-ep.c |  8 +++----
>   drivers/pci/endpoint/pci-epc-core.c           |  5 ++--
>   include/linux/pci-epc.h                       | 13 ++++++++--
>   5 files changed, 64 insertions(+), 22 deletions(-)
> ---
> base-commit: 6f54fb70124423ec417b5efe81f8ced5b9891d62
> change-id: 20260217-master-27db95eb02bd
>
> Best regards,

Re: [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework

[Niklas Cassel]

On Tue, Feb 17, 2026 at 11:24:40AM +0530, Manikanta Maddireddy wrote:
> When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the
> EPF does not allocate backing memory. The host-side pci_endpoint_test driver
> still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to
> BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks
> CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only
> BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no
> longer available for real use (e.g. host DMA via BAR4).
> 
> This series addresses that by:
> 
> 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.
>    BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may
>    leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is
>    for unused BARs that the EPC must disable in .init() and the EPF must not
>    use. pci_epc_get_next_free_bar() treats both as not free.
> 
> 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:
>    BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.
>    Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay
>    enabled so the host can use MSI-X and DMA.
> 
> 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the
>    destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5
>    (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)
>    to the pci_endpoint_test_tbl so the host driver can bind and run tests
>    without corrupting MSI-X or DMA registers.
> 
> 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint
>    (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of
>    64-bit BAR0 and BAR2.
> 
> With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit
> BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.
> 

Hello Manikanta,

There are quite a few things that I think we should implement differently,
please see:
https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u

I'm not trying to take credit from you, for all I care, feel free to take
over the series and add you Co-developed-by on all the patches.

I just though that it would be easier to explain with code rather than a
lot of back and forth.

Hopefully we can send a V2 that includes more detailed BAR_RESERVED
descriptions, that includes what are behind each BAR_RESERVED (including
sizes of each backing MSI-X table/ATU regs/eDMA regs/whatever) in
pcie-tegra194.c.

I also have a Nvidia Jetson Orin Nano board that I can run in EP mode,
so hopefully we can collaborate to get something merged for v7.1.


Kind regards,
Niklas

Re: [PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework

[Manikanta Maddireddy]

On 18/02/26 3:08 am, Niklas Cassel wrote:

> On Tue, Feb 17, 2026 at 11:24:40AM +0530, Manikanta Maddireddy wrote:
>> When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the
>> EPF does not allocate backing memory. The host-side pci_endpoint_test driver
>> still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to
>> BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks
>> CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only
>> BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no
>> longer available for real use (e.g. host DMA via BAR4).
>>
>> This series addresses that by:
>>
>> 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.
>>     BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may
>>     leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is
>>     for unused BARs that the EPC must disable in .init() and the EPF must not
>>     use. pci_epc_get_next_free_bar() treats both as not free.
>>
>> 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:
>>     BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.
>>     Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay
>>     enabled so the host can use MSI-X and DMA.
>>
>> 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the
>>     destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5
>>     (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)
>>     to the pci_endpoint_test_tbl so the host driver can bind and run tests
>>     without corrupting MSI-X or DMA registers.
>>
>> 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint
>>     (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of
>>     64-bit BAR0 and BAR2.
>>
>> With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit
>> BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.
>>
> Hello Manikanta,
>
> There are quite a few things that I think we should implement differently,
> please see:
> https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u
>
> I'm not trying to take credit from you, for all I care, feel free to take
> over the series and add you Co-developed-by on all the patches.
>
> I just though that it would be easier to explain with code rather than a
> lot of back and forth.
>
> Hopefully we can send a V2 that includes more detailed BAR_RESERVED
> descriptions, that includes what are behind each BAR_RESERVED (including
> sizes of each backing MSI-X table/ATU regs/eDMA regs/whatever) in
> pcie-tegra194.c.
>
> I also have a Nvidia Jetson Orin Nano board that I can run in EP mode,
> so hopefully we can collaborate to get something merged for v7.1.
>
>
> Kind regards,
> Niklas

Hi Niklas,


I marked my series "Handled Elsewhere".
I sent new series to define HW reserved BARs.
https://lore.kernel.org/linux-pci/20260222193456.2460963-1-mmaddireddy@nvidia.com/T/#t

Thanks,
Manikanta