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Wysocki" , Danilo Krummrich , Dmitry Baryshkov Subject: Re: [PATCH v4 1/1] regmap: Synchronize cache for the page selector Message-ID: References: <20260218074934.2005168-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Wed, Feb 18, 2026 at 09:30:41AM +0100, Marek Szyprowski wrote: > On 18.02.2026 08:46, Andy Shevchenko wrote: > > If the selector register is represented in each page, its value > > according to the debugfs is stale because it gets synchronized > > only after the real page switch happens. Hence the regmap cache > > initialisation from the HW inherits outdated data in the selector > > register. > > > > Synchronize cache for the page selector just in time. > > > > Before (offset followed by hexdump, the first byte is selector): > > > > // Real registers > > 18: 05 ff 00 00 ff 0f 00 00 f0 00 00 00 > > ... > > // Virtual (per port) > > 40: 05 ff 00 00 e0 e0 00 00 00 00 00 1f > > 50: 00 ff 00 00 e0 e0 00 00 00 00 00 1f > > 60: 01 ff 00 00 ff ff 00 00 00 00 00 00 > > 70: 02 ff 00 00 cf f3 00 00 00 00 00 0c > > 80: 03 ff 00 00 00 00 00 00 00 00 00 ff > > 90: 04 ff 00 00 ff 0f 00 00 f0 00 00 00 > > > > After: > > > > // Real registers > > 18: 05 ff 00 00 ff 0f 00 00 f0 00 00 00 > > ... > > // Virtual (per port) > > 40: 00 ff 00 00 e0 e0 00 00 00 00 00 1f > > 50: 01 ff 00 00 e0 e0 00 00 00 00 00 1f > > 60: 02 ff 00 00 ff ff 00 00 00 00 00 00 > > 70: 03 ff 00 00 cf f3 00 00 00 00 00 0c > > 80: 04 ff 00 00 00 00 00 00 00 00 00 ff > > 90: 05 ff 00 00 ff 0f 00 00 f0 00 00 00 > > > > Fixes: 6863ca622759 ("regmap: Add support for register indirect addressing.") > > Signed-off-by: Andy Shevchenko > > --- > > v4: reworked the approach completely > > > > Marek, Dmitry, > > Please, test on your HW to be sure this will have no side effects > > in your case with LT9611. > > It looks that it ends in infinite recurrent calls after this patch: Thank you for the prompt testing! Can you also _add_ the patch on top from https://lore.kernel.org/all/Z4ppo8wV3nicOfAQ@smile.fi.intel.com/ ? > Insufficient stack space to handle exception! > ESR: 0x0000000096000047 -- DABT (current EL) > FAR: 0xffff8000859bffe0 > Task stack:     [0xffff8000859c0000..0xffff8000859c4000] > IRQ stack:      [0xffff800080030000..0xffff800080034000] > Overflow stack: [0xffff0001fef36140..0xffff0001fef37140] > CPU: 6 UID: 0 PID: 341 Comm: (udev-worker) Not tainted > 6.19.0-next-20260217+ #12215 PREEMPT > Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT) > pstate: 80400005 (Nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) > pc : _regmap_select_page+0x4/0x120 > lr : _regmap_raw_read+0x240/0x340 -- With Best Regards, Andy Shevchenko